Edward F Flaherty

US Patent:

48556238, Aug 8, 1989

Filed:

Nov 5, 1987

Appl. No.:

7/117709

Inventors:

Edward H. Flaherty - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19092
H03K 19094

US Classification:

307475

Abstract:

The specification discloses output buffer circuitry (10) for providing selected output driving characteristics. A plurality of input terminals (13, 24 and 30) receive control and data signals. A plurality of interconnected driver transistors (20, 28, 36 and 42) are connected to an output terminal (22). Drive selector circuitry (16, 18, 38 and 40) is connected between the input terminals (13, 24, and 30) and is responsive to the control signals to vary the electrical interconnection of the driver transistors (20, 28, 36 and 42). The output driving characteristics presented to the output terminal (22) are variable in response to the control signals.

US Patent:

51289440, Jul 7, 1992

Filed:

Jan 11, 1991

Appl. No.:

7/639737

Inventors:

Edward H. Flaherty - Houston TX
Ki S. Chang - Houston TX
Mark W. Tiernan - Stafford TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1100

US Classification:

371 291

Abstract:

An erasable, programmable ROM (10) with three redundant bit-cell arrays (10A, 10B, 10C) includes an error-flagging circuit (30) that detects bit-cell failures and provides notification of each such failure. The error-flagging circuit (30) includes a plurality of XOR gates (32), each receiving the corresponding redundant data bits for one of the bits of an addressed byte, and a NOR gate (36) which receives the outputs from each of the XOR gates (32). Each XOR gate detects when the logic states for the input redundant bits are not identical, indicating a bit-cell failure has occurred, and provides a corresponding logic state output. The NOR gate (36) detects when any of the XOR gates (32) has indicated a bit-cell failure, and generates an error-flag output providing notification of such failure.

US Patent:

52436373, Sep 7, 1993

Filed:

Jun 4, 1992

Appl. No.:

7/893291

Inventors:

Edward H. Flaherty - Houston TX
David A. Van Lehn - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 2100

US Classification:

377 95

Abstract:

A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold. The pulse generator module (20) functions as a modified edge-triggered D flip-flop (21, 23) that triggers in response to paired transitions of CLOCK A and CLOCK B (indicating that the oscillator clock has cycled through both the high and low amplitude thresholds), generating a transition pulse. The pulse counter module (30) includes a pulse counter capacitor (Cl) and a pulse detection transistor (31) that is turned on during each transition pulse to provide a charging path for the pulse counter capacitor, thereby incrementally charging the pulse counter capacitor in response to transition pulses.

US Patent:

47315539, Mar 15, 1988

Filed:

Sep 30, 1986

Appl. No.:

6/913783

Inventors:

David A. Van Lehn - Houston TX
Edward H. Flaherty - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19094
H03K 19003

US Classification:

307443

Abstract:

A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another. The steady-state stage is delayed, so that the noise from the initial transition does not appear at the power supply and reference supply nodes of the steady-state stage.

US Patent:

50346245, Jul 23, 1991

Filed:

May 31, 1989

Appl. No.:

7/359185

Inventors:

Edward H. Flaherty - Houston TX
David A. Van Lehn - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 513

US Classification:

307269

Abstract:

A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold. The pulse generator module (20) functions as a modified edge-triggered D flip-flop (21, 23) that triggers in response to paired transitions of CLOCK A and CLOCK B (indicating that the oscillator clock has cycled through both the high and low amplitude thresholds), generating a transition pulse. The pulse counter module (30) includes a pulse counter capacitor (C1) and a pulse detection transistor (31) that is turned on during each transition pulse to provide a charging path for the pulse counter capacitor, thereby incrementally charging the pulse counter capacitor in response to transition pulses.