Edward Charles Green

US Patent:

60322381, Feb 29, 2000

Filed:

Feb 6, 1998

Appl. No.:

9/020123

Inventors:

Edward Hammond Green - Cary NC
Richard Gerard Hofmann - Cary NC
Mark Michael Schaffer - Cary NC
Dennis Charles Wilkerson - Durham NC

Assignee:

Interantional Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711170

Abstract:

A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.

US Patent:

58840516, Mar 16, 1999

Filed:

Jun 13, 1997

Appl. No.:

8/874639

Inventors:

Mark Michael Schaffer - Cary NC
James N. Dieffenderfer - Apex NC
Edward Hammond Green - Cary NC
Juan Guillermo Revilla - Cary NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1318
G06F 13362

US Classification:

395287

Abstract:

Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.

US Patent:

60473363, Apr 4, 2000

Filed:

Mar 16, 1998

Appl. No.:

9/039645

Inventors:

Edward Hammond Green - Cary NC
Richard Gerard Hofmann - Cary NC
Mark Michael Schaffer - Cary NC
Dennis Charles Wilkerson - Durham NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

710 22

Abstract:

A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.

US Patent:

6055584, Apr 25, 2000

Filed:

Nov 20, 1997

Appl. No.:

8/975540

Inventors:

Jeffrey Todd Bridges - Raleigh NC
Edward Hammond Green - Cary NC
Richard Gerard Hofmann - Cary NC
David Otero - Cary NC
Mark Michael Schaffer - Cary NC
Dennis Charles Wilkerson - Durham NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

710 27

Abstract:

A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.