Edward Charles Haywood

US Patent:

7968452, Jun 28, 2011

Filed:

Jun 30, 2009

Appl. No.:

12/494702

Inventors:

Hanhong Chen - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sunil Shanker - Santa Clara CA, US
Edward Haywood - San Jose CA, US
Sandra Malhotra - San Jose CA, US
Imran Hashim - Saratoga CA, US
Nobi Fuchigami - Santa Clara CA, US
Prashant Phatak - San Jose CA, US
Monica Mathur - San Jose CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 21/4763

US Classification:

438635, 438381, 438399, 438584, 438591, 438656, 438680, 427123, 42724919, 42725532, 42725507, 257E2109

Abstract:

This disclosure provides (a) methods of making an oxide layer (e. g. , a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiOdielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiOdielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

US Patent:

8278735, Oct 2, 2012

Filed:

Oct 8, 2010

Appl. No.:

12/901239

Inventors:

Imran Hashim - Saratoga CA, US
Indranil De - Mountain View CA, US
Tony Chiang - Campbell CA, US
Edward Haywood - San Jose CA, US
Hanhong Chen - San Jose CA, US
Nobi Fuchigami - Santa Clara CA, US
Pragati Kumar - Santa Clara CA, US
Sandra Malhotra - San Jose CA, US
Sunil Shanker - Santa Clara CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 21/02

US Classification:

257532, 257499

Abstract:

This disclosure provides (a) methods of making an oxide layer (e. g. , a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

US Patent:

8486727, Jul 16, 2013

Filed:

Nov 15, 2010

Appl. No.:

12/946846

Inventors:

Hanhong Chen - San Jose CA, US
Edward Haywood - San Jose CA, US
Pragati Kumar - Santa Clara CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

G01R 31/26
H01L 21/66

US Classification:

438 14

Abstract:

Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.

US Patent:

8530322, Sep 10, 2013

Filed:

Dec 16, 2010

Appl. No.:

12/970835

Inventors:

Hanhong Chen - San Jose CA, US
Edward Haywood - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sandra Malhotra - San Jose CA, US
Xiangxin Rui - San Jose CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 21/20

US Classification:

438396, 438397, 438398, 438399, 438785

Abstract:

This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i. e. , to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.

US Patent:

8530348, Sep 10, 2013

Filed:

May 29, 2012

Appl. No.:

13/482573

Inventors:

Sandra G. Malhotra - San Jose CA, US
Hanhong Chen - Milpitas CA, US
Wim Y. Deweerd - San Jose CA, US
Edward L. Haywood - San Jose CA, US
Hiroyuki Ode - Higashihiroshima, JP
Gerald Richardson - San Jose CA, US

Assignee:

Intermolecular, Inc. - San Jose CA
Elpida Memory, Inc. - Tokyo

International Classification:

H01L 21/4763

US Classification:

438624, 438612, 438622, 438625, 438653, 438694

Abstract:

A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

US Patent:

8541828, Sep 24, 2013

Filed:

Nov 5, 2012

Appl. No.:

13/668488

Inventors:

Edward L. Haywood - San Jose CA, US
Sandra G. Malhotra - Fort Collins CO, US
Xiangxin Rui - Campbell CA, US
Sunil Shanker - Santa Clara CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 27/108
H01L 29/76
H01L 29/94
H01L 31/119

US Classification:

257296, 257300, 257760, 257908, 257E21006, 257E21008, 257E21077, 257E2117, 257E21267, 257E21311, 257E21324, 257E21645, 257E21646

Abstract:

Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.

US Patent:

8551851, Oct 8, 2013

Filed:

May 4, 2011

Appl. No.:

13/100538

Inventors:

Hanhong Chen - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sunil Shanker - Santa Clara CA, US
Edward Haywood - San Jose CA, US
Sandra Malhotra - San Jose CA, US
Imran Hashim - Saratoga CA, US
Nobi Fuchigami - Sunnyvale CA, US
Prashant Phatak - San Jose CA, US
Monica Mathur - San Jose CA, US

Assignee:

Intermolecular, Inc. - San Jose CA

International Classification:

H01L 21/20

US Classification:

438381, 29 254, 257E2109, 427123, 42724919, 42725532, 42725537, 4272557, 438399, 438584, 438591, 438635, 438656, 438680

Abstract:

This disclosure provides (a) methods of making an oxide layer (e. g. , a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiOdielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiOdielectric and reduce interface states between TiOand electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

US Patent:

8563392, Oct 22, 2013

Filed:

Dec 5, 2011

Appl. No.:

13/310980

Inventors:

Sandra Malhotra - San Jose CA, US
Wim Deweerd - San Jose CA, US
Edward Haywood - San Jose CA, US
Hiroyuki Ode - Higashihiroshima, JP

Assignee:

Intermolecular, Inc. - San Jose CA
Elpida Memory, Inc. - Tokyo

International Classification:

H01L 21/02

US Classification:

438396, 257E21011

Abstract:

In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

Address:

2749 Taft Ave, Santa Clara, CA 95051

Phone:

(408)6496092

VIN:

JN8AZ2NE8C9021239

Make:

INFINITI

Model:

QX56

Year:

2012