Edward N Salas

US Patent:

44687311, Aug 28, 1984

Filed:

Dec 15, 1981

Appl. No.:

6/330971

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1110

US Classification:

364200

Abstract:

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

US Patent:

45450102, Oct 1, 1985

Filed:

Mar 31, 1983

Appl. No.:

6/480964

Inventors:

Edward R. Salas - Billerica MA
Edwin P. Fisher - N. Abington MA
Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA
Daniel A. Boudreau - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

US Patent:

45876096, May 6, 1986

Filed:

Jul 1, 1983

Appl. No.:

6/510472

Inventors:

Daniel A. Boudreau - Billerica MA
James M. Sandini - Berlin MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1314
G06F 946

US Classification:

364200

Abstract:

A data processing system having a plurality of units includes a shareable unit which is shareable between two or more of the other units. Lock apparatus is provided in the shareable unit to allow a first unit to lock the shareable unit so that no other unit attempting to lock the shareable unit will be permitted access to the shareable unit. The lock apparatus includes means that permit two units desiring to lock the shareable unit to make simultaneously asynchronous requests to lock the shareable unit. The lock apparatus further includes means to permit the unit which has locked the shareable unit to unlock the shareable unit so that it becomes available for a subsequent lock by a unit. The lock apparatus also includes means to allow the shared unit to be accessed by other units not attempting to lock the shareable unit even when the shareable unit is locked.

US Patent:

44930364, Jan 8, 1985

Filed:

Dec 14, 1982

Appl. No.:

6/449702

Inventors:

Daniel A. Boudreau - Billerica MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 946

US Classification:

364200

Abstract:

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay. Logic is provided that allows the predetermined priority levels to be adjusted dynamically as a function of system conditions.

US Patent:

49641298, Oct 16, 1990

Filed:

Dec 21, 1988

Appl. No.:

7/287927

Inventors:

Raymond D. Bowden - Tewksbury MA
Edward R. Salas - Lowell MA
Marc E. Sanfacon - Acton MA
Jeffrey S. Somers - Lowell MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1110

US Classification:

371 402

Abstract:

In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

US Patent:

47870605, Nov 22, 1988

Filed:

Nov 24, 1986

Appl. No.:

6/931956

Inventors:

Daniel A. Boudreau - Billerica MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Bull, Inc. - Minneapolis MN

International Classification:

G06F 1214

US Classification:

364200

Abstract:

A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of a memory module and the module type directly available with minimal intervening logic, a diagnostic process can accurately determine the amount of memory present in the system and reduce the possibility of a failed memory module going undetected. A method is also descibed using these memory module present and module type signals for detecting an attempt by either the central processor or an input/output controller to access a memory location that is not physically present within the data processing system.

US Patent:

46009922, Jul 15, 1986

Filed:

Dec 14, 1982

Appl. No.:

6/449703

Inventors:

Daniel A. Boudreau - Billerica MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 946
G06F 1516

US Classification:

364200

Abstract:

A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

US Patent:

46547886, Mar 31, 1987

Filed:

Jun 15, 1983

Appl. No.:

6/504751

Inventors:

Daniel A. Boudreau - Billerica MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1314
G06F 1200
G06F 300

US Classification:

364200

Abstract:

A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses. Priority resolver circuits award access to main memory on a predetermined priority basis. Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits. The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors.