Edward Frank Scott

US Patent:

D632927, Feb 22, 2011

Filed:

Feb 5, 2010

Appl. No.:

29/348759

Inventors:

Edward L. Scott - Palmdale CA, US

International Classification:

0701

US Classification:

D 7540, D7629, D9504

US Patent:

44358075, Mar 6, 1984

Filed:

Jan 27, 1982

Appl. No.:

6/343109

Inventors:

Edward W. Scott - Glendale CA
Daniel B. Goetschel - Troy NY

International Classification:

G06F 1110

US Classification:

371 50

Abstract:

An error correcting system involves the addition of parity type correction bits to each word in a series of digital word forming data to be transmitted or processed. When a person is passing an orchard where a field of partially grown trees are planted, you can look directly down the rows of trees perpendicular to the side of the field, and you can also look at an angle 45 degrees forward and down an open path 45 degrees to the rear of your path along the side of the orchard. In the present system, the error correction parity bits are summed over digits representing more then one vector through the words of data information, which are quite similar to the prospect along three different vectors in an orchard, as mentioned above. Following transmission through a data link in which errors may be introduced by the reversal of certain bits, the bits are summed along the same vectors in an error correcting circuit, and a pattern of error correction "flag" bits is associated with each word with the error correction bits representing sums along vectors which did not have the predetermined parity. A first error correction circuit is provided for correcting single errors within the pattern covered by the vectors; and a second multiple error correcting circuit receives the data from the first error correction circuit after the single errors have been corrected both in the data, the associated correction bits, and in the associated error detection bits, and the residual multiple errors are then corrected in this second error detection circuit.