Edwin E Klingman

US Patent:

6425122, Jul 23, 2002

Filed:

Jun 23, 1999

Appl. No.:

09/339010

Inventors:

Edwin E. Klingman - San Gregorio CA 94074

International Classification:

G06F 944

US Classification:

717124, 717127

Abstract:

A method for controlling the execution of a sole target processor or a target processor embedded in a chain of target processor units by a host-processor. The target processor unit includes a shared control register, a shared memory accessible by both the target and host processor and a code memory alterable by the host processor and containing the target processor program. The shared control register includes a single step flag to indicate that the host processor is setting the single step mode of operation for the target processor. The shared control register further includes a clock inhibit flag to permit the target processor to stop execution. Clearing the clock inhibit flag releases the target processor to execute the program in the code memory during which the target processor tests the single step flag to determine whether it should stop execution after one instruction has been executed. If the flag is set the target processor reports its instruction pointer to the host processor via the shared memory and stops.

US Patent:

6584525, Jun 24, 2003

Filed:

Nov 19, 1999

Appl. No.:

09/443944

Inventors:

Edwin E. Klingman - San Gregorio CA 94074

International Classification:

G06F 1300

US Classification:

710118, 710305, 710101

Abstract:

A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLDs and FPGAs).

US Patent:

6789212, Sep 7, 2004

Filed:

Mar 20, 2000

Appl. No.:

09/531911

Inventors:

Edwin E. Klingman - San Gregorio CA 94074

International Classification:

G06F 1100

US Classification:

714 9, 714 3, 714 12

Abstract:

A system is described capable of excising individual cells in an N-dimensional array and healing the array connectivity without manual intervention. Thus cells that fail can be deleted and the array remain viable, although possibly requiring re-synchronization procedures to be performed. The system allows either replacement of bad cells or bypassing of bad cells, with appropriate cost and operational differences. Both level sensitive and edge sensitive excision mechanisms are described and the consequences of each discussed. The invention applies to processor arrays with one cell per physical chip or many cells per chip, and handles uni-directional or bi-directional data flows, and is generally both interface independent and technology independent.

US Patent:

6928505, Aug 9, 2005

Filed:

Sep 26, 2000

Appl. No.:

09/670954

Inventors:

Edwin E. Klingman - San Gregorio CA, US

International Classification:

G06F013/00

US Classification:

710305, 710110, 710313

Abstract:

A device controller for connecting a function engine that supports an application to a packet-switched serial bus to which a host device is connected. The interface device includes a serial interface engine for transferring packets between the serial bus and the function engine and an interfacing device that employs a plurality of state machines in a device configuration module. The state machines of the device configuration module operate to configure the interfacing device and make that configuration known to the host. Additionally, for each interface of the function engine that is a group of state machines, at least one of which transfers data between the serial interface engine and the function engine. In one embodiment the serial bus is the USB and the configuration module conforms to the configuration protocol of the USB. As an additional aspect of the invention multiple configurations are supported by the device configuration module.

US Patent:

6976069, Dec 13, 2005

Filed:

Jan 21, 2000

Appl. No.:

09/488977

Inventors:

Edwin E. Klingman - San Gregorio CA, US

International Classification:

G06F015/173

US Classification:

709224, 370248, 379106

Abstract:

An apparatus and method of measuring the performance of a computer network by determining transit times of packets between two selected sites connected by the computer network and the public switched telephone network and deriving from those transit times a measure of the performance of the computer network. Software establishes a network connection and a circuit switched connection between the two selected sites. A pair of messages is sent, at the same or nearly the same time, over the network connection and the circuit-switched connection and the transit time for a one way trip over the network connection is derived from the trips over the network and circuit-switched connections. This furnishes a measurement from which performance statistics of the computer network can be derived.

US Patent:

7043568, May 9, 2006

Filed:

Sep 26, 2000

Appl. No.:

09/670509

Inventors:

Edwin E. Klingman - San Gregorio CA, US

International Classification:

G06F 3/00
G06F 13/00
G06F 13/14
G06F 12/10
H04L 12/28

US Classification:

710 8, 710 9, 710 10, 710 14, 710107, 710110, 710306, 710310, 710313

Abstract:

A selection system for configuring a device controller. The selection system includes a plurality of state machines each of which has a portion of the configuration information needed to inform a host, connected to the device controller via a serial bus, of the device configuration as well as the configuration, interface and endpoint information. The selection system also includes a selection circuit that selects one of the plurality of state machines in response to a selection code that can be set by a user manually or automatically by programming are register. The manual setting of the selection code is by means of a set of configurable pins which are selected as the default source of the selection code by the selection system. If there are available a variety of device configurations and associated interface and endpoint configurations, the selection system selects one of the device configurations and the associated other configuration information in response to the same selection code, thereby maintaining consistency between the device configuration information and the other associated configuration information.

US Patent:

7187662, Mar 6, 2007

Filed:

Sep 1, 1999

Appl. No.:

09/387938

Inventors:

Edwin E. Klingman - San Gregorio CA, US

International Classification:

H04Q 11/00

US Classification:

370270

Abstract:

A table driven call management system for an organization having a plurality of departments and agent. The call management system is capable of supporting local and remote agents each of which can have the same degree of access to the organization's information. Calls are received by the call management system and handled according to a table describing a department in the organization. If an agent for the department is available according to the table, the call is transferred to the agent, either local or remote. If the agent is not available, the call is transferred to another department according to an entry in the table. If no department has an agent available to take the call, a caller message is recording in a department mailbox or a default mail box or the call is transferred to an available operator. Call management software is object oriented having only two objects, a call manager object and an array of call objects, each call object including a department table with which the call is currently associated. The software is flexible so that the department tables can be tailored to the organization and the handling policy can be easily changed.

US Patent:

7594232, Sep 22, 2009

Filed:

Apr 23, 2004

Appl. No.:

10/831649

Inventors:

Edwin E. Klingman - San Gregorio CA, US

International Classification:

G06F 12/02

US Classification:

718104, 711153, 711156, 711170, 711173, 718 1, 718100, 718106, 718107

Abstract:

Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.