Ellis E Chang

US Patent:

7570796, Aug 4, 2009

Filed:

Nov 20, 2006

Appl. No.:

11/561659

Inventors:

Khurram Zafar - San Jose CA, US
Sagar Kekare - Plano TX, US
Ellis Chang - Saratoga CA, US
Allen Park - San Jose CA, US
Peter Rose - Boulder Creek CA, US

Assignee:

KLA-Tencor Technologies Corp. - Milpitas CA

International Classification:

G06K 9/00

US Classification:

382144, 382145, 382151

Abstract:

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

US Patent:

7571422, Aug 4, 2009

Filed:

Sep 18, 2007

Appl. No.:

11/857301

Inventors:

Michael Adel - Zichron Ya'akov, IL
Ellis Chang - Saratoga CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 19, 716 2, 716 4, 716 18

Abstract:

The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.

US Patent:

7711514, May 4, 2010

Filed:

Aug 10, 2007

Appl. No.:

11/837208

Inventors:

Allen Park - San Jose CA, US
Ellis Chang - Saratoga CA, US

Assignee:

KLA-Tencor Technologies Corp. - Milpitas CA

International Classification:

G01M 19/00
G06F 11/30

US Classification:

702123, 382145, 382149, 702 81, 702185

Abstract:

Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology.

US Patent:

7904845, Mar 8, 2011

Filed:

Dec 5, 2007

Appl. No.:

11/950961

Inventors:

Christophe Fouquet - Sunnyvale CA, US
Gordon Abbott - Pleasanton CA, US
Ellis Chang - Saratoga CA, US
Zain K. Saidin - San Mateo CA, US

Assignee:

KLA-Tencor Corp. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 702 81, 702 82, 702 83, 702108, 702109, 702117, 702118, 324765

Abstract:

Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

US Patent:

8139844, Mar 20, 2012

Filed:

Apr 14, 2008

Appl. No.:

12/102343

Inventors:

Yan Xiong - Sunnyvale CA, US
Jianxin Zhang - Santa Clara CA, US
Ellis Chang - Saratoga CA, US

Assignee:

KLA-Tencor Corp. - San Jose CA

International Classification:

G06K 9/00

US Classification:

382145, 382147

Abstract:

Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect.

US Patent:

8194968, Jun 5, 2012

Filed:

Jan 7, 2008

Appl. No.:

11/970294

Inventors:

Allen Park - San Jose CA, US
Peter Rose - Boulder Creek CA, US
Ellis Chang - Saratoga CA, US
Brian Duffy - San Jose CA, US
Mark McCord - Mountain View CA, US
Gordon Abbott - Pleasanton CA, US

Assignee:

KLA-Tencor Corp. - San Jose CA

International Classification:

G06K 9/00

US Classification:

382145

Abstract:

Various methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions are provided. One computer-implemented method includes using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions. The one or more defect-related functions include one or more post-mask, defect-related functions.

US Patent:

8559001, Oct 15, 2013

Filed:

Jan 5, 2011

Appl. No.:

12/984679

Inventors:

Ellis Chang - Saratoga CA, US
Amir Widmann - Hof HaCarmel, IL
Allen Park - San Jose CA, US

Assignee:

KLA-Tencor Corporation - Milpitas CA

International Classification:

G01N 21/00
G01R 31/26

US Classification:

3562375, 3562371, 702 40, 382141, 382145, 382151, 438 14, 438 16, 25055939, 2505593

Abstract:

Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

US Patent:

8594823, Nov 26, 2013

Filed:

Jul 12, 2010

Appl. No.:

12/919757

Inventors:

Allen Park - San Jose CA, US
Ellis Chang - Saratoga CA, US
Masami Aoki - Kanagawa, JP
Chris Chih-Chien Young - Palo Alto CA, US
Martin Plihal - Pleasanton CA, US
Michael John Van Riet - Sunnyvale CA, US

Assignee:

KLA—Tencor Corporation - Milpitas CA

International Classification:

G06F 19/00
H01L 21/66

US Classification:

700110, 700121

Abstract:

A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively.