Eric M Ajimine

US Patent:

6771545, Aug 3, 2004

Filed:

Jan 29, 2003

Appl. No.:

10/353558

Inventors:

Edward Hsia - Saratoga CA
Eric Ajimine - Saratoga CA
Darlene G. Hamilton - San Jose CA
Pauling Chen - Saratoga CA
Ming-Huei Shieh - Cupertino CA
Mark W. Randolph - San Jose CA
Edward Runnion - Santa Clara CA
Yi He - Fremont CA

Assignee:

Advanced Micro Devices Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 3651853, 36518511

Abstract:

An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

US Patent:

6901010, May 31, 2005

Filed:

Apr 8, 2002

Appl. No.:

10/119366

Inventors:

Darlene G. Hamilton - San Jose CA, US
Eric M. Ajimine - San Jose CA, US
Binh Le - San Jose CA, US
Edward Hsia - Saratoga CA, US
Ken Tanpairoj - Palo Alto CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C007/00

US Classification:

36518522, 36518524, 36518529, 36518533, 365218

Abstract:

An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

US Patent:

6735114, May 11, 2004

Filed:

Feb 4, 2003

Appl. No.:

10/357879

Inventors:

Darlene G. Hamilton - San Jose CA
Eric M. Ajimine - Saratoga CA
Ming-Huei Shieh - Cupertino CA
Lee Cleveland - Santa Clara CA
Edward F. Runnion - Santa Clara CA
Mark W. Randolph - San Jose CA
Sameer S. Haddad - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518503, 36518512, 3651852, 36518529

Abstract:

A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.