Eric Noel Cartagena

US Patent:

6404038, Jun 11, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/517292

Inventors:

Eric N. Cartagena - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 27082

US Classification:

257586, 257511, 257565

Abstract:

A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire substrate. The silicon is improved using double solid phase epitaxy. The silicon is then patterned and implanted with P+-type and N+-type dopants. Subsequently a micrometer scale N-type layer is grown that acts as the intrinsic base for both an PNP transistor and as the collector for an NPN transistor. The extrinsic base for the NPN is then formed and the emitter, collector and ohmic contact regions are next selectively masked and implanted. Conductive metal is then formed between protecting oxide to complete the complementary vertical bipolar junction transistors.

US Patent:

6504411, Jan 7, 2003

Filed:

Oct 30, 2001

Appl. No.:

10/021150

Inventors:

Eric Noel Cartagena - San Diego CA

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H03K 3037

US Classification:

327199, 327217, 327526

Abstract:

A redundant latch circuit resistant to SEUs includes a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. The majority voting circuit indicates a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. The feedback reset circuit may have inputs connected to the outputs of the latches, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs.

US Patent:

6759303, Jul 6, 2004

Filed:

Mar 5, 2002

Appl. No.:

10/092065

Inventors:

Eric N. Cartagena - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 218228

US Classification:

438322, 438340, 438342, 438353, 438355

Abstract:

A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire substrate. The silicon is improved using double solid phase epitaxy. The silicon is then patterned and implanted with P+-type and N+-type dopants. Subsequently a micrometer scale N-type layer is grown that acts as the intrinsic base for both an PNP transistor and as the collector for an NPN transistor. The extrinsic base for the NPN is then formed and the emitter, collector and ohmic contact regions are next selectively masked and implanted. Conductive metal is then formed between protecting oxide to complete the complementary vertical bipolar junction transistors.

US Patent:

53626591, Nov 8, 1994

Filed:

Apr 25, 1994

Appl. No.:

8/232914

Inventors:

Eric N. Cartagena - Chula Vista CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A method is provided for manufacturing a bipolar transistor, comprising the teps of: 1) abutting a polished surface of a substantially single crystal silicon wafer with a polished surface of an insulating substrate; 2) heating the abutting silicon wafer and insulating substrate at about 200. degree. C. for about 30 minutes to form a bonded wafer having a silicon layer; 3) forming a silicon island from the silicon layer; 4) ion implanting a first dopant species having a first conductivity into the silicon island to form a base region in the silicon island; 5) ion implanting a second dopant species having a second conductivity opposite the first conductivity into the silicon island to form an emitter region and a collector region in the silicon island; 6) ion implanting a third dopant species having the first conductivity into the base region of the silicon island; 7) heating the bonded wafer at a temperature of about 800. degree. C. to activate the first, second, and third dopant species and to repair ion implanting damage to the silicon island; 8) forming electrical contacts to the base, emitter, and collector regions; and 9) forming an oxide layer over the electrical contacts to passivate the electrical contacts.

US Patent:

53745671, Dec 20, 1994

Filed:

May 20, 1993

Appl. No.:

8/065321

Inventors:

Eric N. Cartagena - Chula Vista CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A method for fabricating low leakage current bipolar junction transistors of silicon-on-sapphire for efficient use in operational amplifiers utilizes all implant technology, improved silicon conditioning processing, and low temperature annealing.

US Patent:

56416911, Jun 24, 1997

Filed:

Apr 3, 1995

Appl. No.:

8/415389

Inventors:

Eric N. Cartagena - Chula Vista CA
Howard W. Walker - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01L 21265

US Classification:

438311

Abstract:

A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.

US Patent:

57147930, Feb 3, 1998

Filed:

Aug 21, 1996

Appl. No.:

8/700894

Inventors:

Eric N. Cartagena - Chula Vista CA
Howard W. Walker - San Diego CA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washiington DC

International Classification:

H01L 218228

US Classification:

257507

Abstract:

A method is described for fabricating a complementary, vertical bipolar sconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.