Eric H Chang

US Patent:

7277346, Oct 2, 2007

Filed:

Dec 14, 2004

Appl. No.:

11/012877

Inventors:

Irfan Rahim - San Jose CA, US
Peter J. McElheny - Morgan Hill CA, US
Eric Choong-Yin Chang - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 17/18

US Classification:

3652257, 326 39, 326 10, 326 12, 326 13, 365200, 365201, 36518509

Abstract:

A semiconductor system and method for repairing failures of a packaged integrated circuit system are provided. The method includes detecting a failure associated with a packaged integrated circuit system after the packaged integrated circuit system is packaged, and repairing the failure by activating a redundancy circuit in the packaged integrated circuit system and deactivating a defective circuit associated with the failure. The process for repairing the failure includes applying a repair voltage to a polysilicon fuse to change a conductivity state of the polysilicon fuse from a first state to a second state. In another embodiment, the polysilicon fuse is replaced by a metal fuse, an anti-fuse, or a non-volatile random access memory.

US Patent:

7319341, Jan 15, 2008

Filed:

Aug 28, 2003

Appl. No.:

10/653045

Inventors:

Michael Harms - Pleasanton CA, US
Eric C. Chang - Cupertino CA, US
Paul Tracy - Sunnyvale CA, US
John DiCosola - Pleasanton CA, US
Mandrita Brahmachari - Milpitas CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 31/26

US Classification:

324765

Abstract:

The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i. e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.

US Patent:

7671579, Mar 2, 2010

Filed:

Sep 7, 2006

Appl. No.:

11/470898

Inventors:

Yan Chong - San Jose CA, US
Joseph Huang - Morgan Hill CA, US
Chiakang Sung - Milpitas CA, US
Eric Choong-Yin Chang - Cupertino CA, US
Peter Boyle - Mountain View CA, US
Adam J. Wright - Saratoga CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 23/175
G08B 23/00

US Classification:

324 7654, 324 7635, 340527

Abstract:

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

US Patent:

7884619, Feb 8, 2011

Filed:

Sep 24, 2009

Appl. No.:

12/566157

Inventors:

Yan Chong - San Jose CA, US
Joseph Huang - Morgan Hill CA, US
Chiakang Sung - Milpitas CA, US
Eric Choong-Yin Chang - Cupertino CA, US
Peter Boyle - Mountain View CA, US
Adam J. Wright - Saratoga CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 35/00
G01R 23/175
G08B 23/00
H03L 7/00

US Classification:

324601, 324 7654, 340527, 327153

Abstract:

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

US Patent:

20110221497, Sep 15, 2011

Filed:

Feb 1, 2011

Appl. No.:

13/019277

Inventors:

Yan Chong - San Jose CA, US
Joseph Huang - Morgan Hill CA, US
Chiakang Sung - Milpitas CA, US
Eric Choong-Yin Chang - Cupertino CA, US
Peter Boyle - Mountain View CA, US
Adam J. Wright - Saratoga CA, US

International Classification:

H03L 7/00
H03H 11/26

US Classification:

327161, 327284

Abstract:

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

US Patent:

61343242, Oct 17, 2000

Filed:

May 29, 1997

Appl. No.:

8/865307

Inventors:

James Bohannon - San Jose CA
Eric Chang - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04L 900

US Classification:

380 4

Abstract:

A technique for mass distributing software products, especially integrated circuit design tools and design libraries, while allowing only a selected portion of the products to be loaded onto and used on a computer. One or more volumes of CD-ROM contains one or more software products, each of which are encrypted with a key code. The CD-ROMs are mass distributed to customers. A separate configuration file, uniquely configured for each customer, contains a list of only the selected portion of software products, and contains the key codes for decrypting only those products. A loader module is provided for controlling the decryption and loading of only the selected portion of products, based on information in the configuration file. Each software product is hierarchically arranged by class, file set and file, and files may be shared between products.

US Patent:

20190115925, Apr 18, 2019

Filed:

May 15, 2018

Appl. No.:

15/980467

Inventors:

- Redwood Shores CA, US
Frankie Y. Liu - Palo Alto CA, US
Suwen Yang - Mountain View CA, US
Ziad Saleh Shehadeh - Mountain View CA, US
Eric Y. Chang - San Mateo CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

H03L 7/081
H03L 7/197
H03L 7/099

Abstract:

We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

US Patent:

20180259797, Sep 13, 2018

Filed:

May 8, 2018

Appl. No.:

15/974313

Inventors:

- Redwood Shores CA, US
Eric Y. Chang - San Mateo CA, US
Frankie Y. Liu - Palo Alto CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G02F 1/01
G02F 1/313
G02F 1/025

Abstract:

In an optical device, a ring-resonator modulator, having an adjustable resonance (center) wavelength, receives an optical signal that includes a carrier wavelength from an input-output optical waveguide. Then, a monitoring mechanism monitors a performance metric (such as an average power or a signal swing) of a monitor optical signal from the ring-resonator modulator. Moreover, control logic in the optical device adjusts the resonance wavelength based on the monitored performance metric so that the resonance wavelength is locked to the carrier wavelength. In particular, the control logic may apply a change to an adjustment signal that is provided to the ring-resonator modulator. If the change increases the performance metric, the control logic may continue to modify the resonance wavelength. Otherwise, the control logic may modify the resonance wavelength by applying one or more changes, having an opposite sign to the change, to the adjustment signal.