Eric J Conway

US Patent:

6604060, Aug 5, 2003

Filed:

Jun 29, 2000

Appl. No.:

09/607023

Inventors:

Charles P. Ryan - Phoenix AZ
Eric E. Conway - Mesa AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1130

US Classification:

702186, 709224, 714 12

Abstract:

In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors ( ) sharing an L2 cache ( ) differs from the time it takes for those signals to travel between processors ( ) not sharing the same L2 cache ( ). This difference, or DELTA, is dynamically computed by computing ( ) the time it takes for a invalidate cache line cache command to travel between a local processor ( ) and a master processor ( ). This computation ( ) is then made for the time it takes the signal to travel between a remote processor ( ) and the master processor ( ). The difference ( ) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment ( ).

US Patent:

20050097485, May 5, 2005

Filed:

Oct 29, 2003

Appl. No.:

10/697406

Inventors:

Russell Guenthner - Glendale AZ, US
David Selway - Phoenix AZ, US
Clinton Eckard - McMinnville TN, US
Charles Ryan - Phoenix AZ, US
Eric Conway - Mesa AZ, US

International Classification:

G06F009/45
G06F017/50

US Classification:

716006000, 716018000

Abstract:

A methodology for improving the timing of specific critical paths in a Field Programmable Gate Array (FPGA) implementation of a logic circuit without significantly affecting the timing of other logic paths. The method utilizes logic replication and specific guidelines for placement of the logic gates involved in a critical path to optimize the timing of that critical path. The logic gates involved in a critical path are either replicated and placed, or simply moved, in order to implement the desired logic with nearly the shortest total distance for routing of signals involved in the critical path. The optimization is carried out with relatively little impact on the timing of other paths and is applicable to FPGAs in which the signal delay between any source and gate is relatively independent of the fanout of the source signal to any other loads.

US Patent:

6351807, Feb 26, 2002

Filed:

Sep 25, 1998

Appl. No.:

09/160904

Inventors:

Ron W. Yoder - Mesa AZ
Russell W. Guenthner - Glendale AZ
William A. Shelly - Phoenix AZ
Eric Earl Conway - Mesa AZ
Boubaker Shaiek - Phoenix AZ
Claude Rabel - Phoenix AZ

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 935

US Classification:

712228, 712213, 712215, 711208, 711209, 709108

Abstract:

A processor ( ) in a data processing system simultaneously loads multiple registers ( ) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal ( ) along with the register write signal ( ) when block writing the single value to the set of registers ( ). Register address lines ( ) are decoded in two sets: a first set of decoded address lines ( ) specifying a block of registers; and the second set ( ) specifying one register in the block of registers. When the register block write signal ( ) is asserted during a register write, the second set of decoded address lines ( ) are ignored, and all registers in the block of registers ( ) selected by the first set of decoded address lines ( ) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer ( ) to each register bit, or by disabling ( ) the feedback path ( ) in each register bit during block writes.