Eric Rodgers Daniel

US Patent:

7544072, Jun 9, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/926274

Inventors:

Brandon Rubenstein - Loveland CO, US
Roger Nattkemper - Antelope CA, US
Eric Daniel - Sacramento CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H01R 13/64

US Classification:

439135, 439381

Abstract:

An apparatus for protecting an array of pins of an electronic device is provided. The apparatus includes a pin protector defining an array of holes therethrough, wherein each hole is configured to receive one of the pins. The apparatus also comprises a spring element configured to bias the pin protector away from the electronic device toward an end of each of the pins. The spring element is also configured to allow the pin protector to be retracted toward the electronic device to expose the pins for insertion into a socket or similar component.

US Patent:

20130208410, Aug 15, 2013

Filed:

Oct 28, 2010

Appl. No.:

13/822702

Inventors:

Brandon Rubenstein - Loveland CO, US
Roger Nattkemper - Antelope CA, US
Eric R. Daniel - Sacramento CA, US

International Classification:

H05K 7/10
G06F 1/16

US Classification:

36167902, 439331

Abstract:

A land grid array socket assembly comprises a plurality of cells, with each cell comprising an insulative body having a top surface, and contact conductor that has a first portion that extends from a board contact point up to and beyond the top surface to a contact bend, and a second portion that extends from the contact bend to terminate below the top surface and within the insulative body.

US Patent:

60405309, Mar 21, 2000

Filed:

Dec 5, 1997

Appl. No.:

8/986078

Inventors:

Robert J. Wharton - Rocklin CA
Eric R. Daniel - Sacramento CA
Joseph D. Brown - Rocklin CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01R 909

US Classification:

174261

Abstract:

A printed circuit board can be used as a test card. The printed circuit board has a first image and a second image. The first image includes a first array pattern for attaching a package, a first power plane, and a first ground plane. The second image includes a second array pattern for attaching a package, a second power plane, and a second ground plane. A first routing area between the first image and the second image electrically and physically isolates the first power plane from the second power plane. The first routing area also physically isolates the first ground plane from the second ground plane. A first single trace extends through the first routing area. The first single trace electrically connects the first ground plane to the second ground plane.