Eric L Hendrickson

age ~44

from La Palma, CA

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Also known as:

Eric Lee Hendrickson
Eric Lee Henderickson

Connected to:

Eric Hendrickson Phones & Addresses

La Palma, CA
Downey, CA
Laguna Hills, CA
Fountain Valley, CA
Pflugerville, TX
Austin, TX
Orange, CA
West Los Angeles, CA
Fountain Vly, CA
18601 Auburn Ave, Santa Ana, CA 92705

Work

Company:

Intel corporation
Aug 2011
Position:

Xeon interconnect and memory controller design lead

Education

School / High School:

UCLA- Los Angeles, CA
2004
Specialities:

BS in Computer Science and Engineering

Ranks

Licence:

Wisconsin - Good Standing
Date:

1987

Lawyers & Attorneys

Eric Daniel Hendrickson - Lawyer

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Address:

Werner, Lindgren & Johnson, S.C.
(920)9827205

Licenses:

Wisconsin - Good Standing 1987

Education:

University of Wisconsin Law School
Degree - JD - Juris Doctor - Law
Graduated - 1987
University of Wisconsin, Madison
Degree - BBA - Business Administration
Graduated - 1984

Specialties:

Family - 100%

Name / Title

Company / Classification

Phones & Addresses

Eric Hendrickson

ROSS HALL INVESTMENTS LLC

Eric Hendrickson

ROSSLYN INVESTMENTS LLC

Eric Hendrickson

ACCUPRO, LLC

Eric Hendrickson

CRESTLAND PARK RENAISSANCE, LTD

Us Patents

Technique For Promoting Determinism Among Multiple Clock Domains
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US Patent:

8312309, Nov 13, 2012
Filed:

Mar 5, 2008
Appl. No.:

12/042985
Inventors:

Eric L. Hendrickson - Fountain Valley CA, US
Sanjoy Mondal - Austin TX, US
Larry Thatcher - Austin TX, US
William Hodges - Austin TX, US
Lance Hacking - Austin TX, US
Sankaran Menon - Austin TX, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 1/12
G06F 11/00
US Classification:

713400, 713502, 714 34
Abstract:

A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Packed Write Completions
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US Patent:

20160188500, Jun 30, 2016
Filed:

Dec 25, 2014
Appl. No.:

14/583147
Inventors:

- Santa Clara CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bill Nale - Livermore CA, US
Robert G. Blankenship - Tacoma WA, US
Jeff Willey - Timnath CO, US
Eric L. Hendrickson - Downey CA, US
International Classification:

G06F 13/16
G11C 7/10
Abstract:

A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

Error Handling In Transactional Buffered Memory
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US Patent:

20160179610, Jun 23, 2016
Filed:

Dec 20, 2014
Appl. No.:

14/578413
Inventors:

- Santa Clara CA, US
Bill Nale - Livermore CA, US
Robert G. Blankenship - Tacoma WA, US
Eric L. Hendrickson - Downey CA, US
International Classification:

G06F 11/08
G06F 11/16
Abstract:

Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

Resumes

Ilqa Um

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Position:

Contractor at Government

Location:

Mckinney, Texas

Industry:

Law Enforcement

Work:

Government - Dallas/Fort Worth Area since Jan 2012
Contractor
Drive America Holdings Jul 2009 - Jul 2011
Workforce Analyst
Countrywide - Plano Mar 2003 - Mar 2009
Team Manager Business Analysis
Bank of America (formerly Countrywide Financial Corporation) Mar 2003 - Mar 2009
Business Analyst II/Emergency Response Team Leader
Sears District Service Center Apr 1999 - Aug 2002
Special Teams Manager

Education:

American Military University 2008 - 2010
Masters, Emergency Management/Homeland Security American Military University 2008 - 2010
Masters Degree, Emergency Management Capstone University of North Texas 2008
Bachelors Degree, Emergency Management & Disaster Planning North Harris College 1996
Associates Degree, Criminal Justice

Asic Design Engineer At Intel Corporation

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Position:

ASIC Design Engineer at Intel Corporation

Location:

Orange County, California Area

Industry:

Semiconductors

Work:

Intel Corporation since Aug 2011
ASIC Design Engineer
QLogic Jun 2008 - Aug 2011
ASIC Design Engineer
iStor Networks, Inc. Jul 2007 - Jun 2008
ASIC Design Verification Engineer
Intel Corporation Jul 2005 - Jul 2007
Debug Tools Engineer
Advanced Micro Devices Jul 2004 - Jul 2005
Systems Debug Engineer

Education:

University of California, Irvine 2010 - 2013
MS, Computer Engineering University of California, Los Angeles 1999 - 2004
BSE, Computer Science and Engineering fvhs

Professional

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Location:

United States

Asic Design Engineer At Qlogic

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Position:

ASIC Design Engineer at QLogic

Location:

Orange County, California Area

Industry:

Semiconductors

Work:

QLogic
ASIC Design Engineer

Eric Hendrickson

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Location:

United States

Eric Hendrickson Laguna Hills, CA

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Work:

Intel Corporation

Aug 2011 to 2000
Xeon Interconnect and Memory Controller Design Lead Qlogic Corp

Jul 2008 to Aug 2011
ASIC Design/Verification Staff Engineer Istor Networks

Sep 2007 to Jun 2008
Associate Principal Design Engineer Intel Corp

Jun 2005 to Sep 2007
Post Silicon Debug Tools Engineer Advanced Micro Devices

Jun 2004 to Jun 2005
Systems Debug Engineer

Education:

UCLA
Los Angeles, CA
2004
BS in Computer Science and Engineering