Eric D Hendrickson

US Patent:

7193451, Mar 20, 2007

Filed:

Jan 24, 2005

Appl. No.:

11/041766

Inventors:

Eric O. Hendrickson - Lakeville MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

H03K 3/00

US Classification:

327199, 327 34, 327197, 327198, 327427, 327428

Abstract:

A method and system for reducing glitch effects in combinational logic is presented. If combinational logic incurs a particle-induced single event transient (SET) signal, a glitch reducing circuit, which is connected in a signal path between the combinational logic and downstream logic, will prevent the SET from propagating to the downstream logic. The glitch reducing circuit functions as a signal filter that provides a SET-filtered drive signal to downstream logic. The glitch reducing circuit receives both the input to the combinational logic and the output from the combinational logic. The input acts to enable or disable the glitch reducing circuit, so that for certain input values, the glitch reducing circuit passes the logic output signal to downstream logic, and for other input values, the glitch reducing circuit blocks the output signal from passing to downstream logic.

US Patent:

8312309, Nov 13, 2012

Filed:

Mar 5, 2008

Appl. No.:

12/042985

Inventors:

Eric L. Hendrickson - Fountain Valley CA, US
Sanjoy Mondal - Austin TX, US
Larry Thatcher - Austin TX, US
William Hodges - Austin TX, US
Lance Hacking - Austin TX, US
Sankaran Menon - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/12
G06F 11/00

US Classification:

713400, 713502, 714 34

Abstract:

A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

US Patent:

20170322841, Nov 9, 2017

Filed:

Mar 17, 2017

Appl. No.:

15/462185

Inventors:

- Santa Clara CA, US
Bill Nale - Livermore CA, US
Robert G. Blankenship - Tacoma WA, US
Eric L. Hendrickson - Irvine CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/08
H04L 1/00
G06F 13/00
G06F 11/16
G06F 11/16
H04L 1/18
G06F 11/16

Abstract:

Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.