Eric James Magnusson

US Patent:

6496792, Dec 17, 2002

Filed:

Jul 6, 1998

Appl. No.:

09/111126

Inventors:

Eric J. Magnusson - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1750

US Classification:

703 27, 703 17, 714 37, 714 45

Abstract:

A method and apparatus for a transaction checking for system architecture validation are provided. Tracking data is received from trackers in the system. The tracking data is parsed to construct queues. These queues are compared with each other. For one embodiment, the queues are further compared with predicted behavior of the element that was tested. Discrepancies between the queues and the queue and predicted behavior are flagged.

US Patent:

60147555, Jan 11, 2000

Filed:

Aug 12, 1996

Appl. No.:

8/700676

Inventors:

Steven E. Wells - Citrus Heights CA
Eric J. Magnusson - Orangevale CA
Robert N. Hasbun - Shingle Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 8

Abstract:

A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

US Patent:

54737532, Dec 5, 1995

Filed:

Oct 30, 1992

Appl. No.:

7/969749

Inventors:

Steven E. Wells - Citrus Heights CA
Eric J. Magnusson - Orangevale CA
Robert N. Hasbun - Shingle Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100
G11C 2900

US Classification:

39518203

Abstract:

A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

US Patent:

55771947, Nov 19, 1996

Filed:

Aug 7, 1995

Appl. No.:

8/511990

Inventors:

Steven E. Wells - Citrus Heights CA
Eric J. Magnusson - Orangevale CA
Robert N. Hasbun - Shingle Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128
G06F 1100

US Classification:

39518206

Abstract:

A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

US Patent:

53696166, Nov 29, 1994

Filed:

Mar 7, 1994

Appl. No.:

8/207228

Inventors:

Steven E. Wells - Citrus Heights CA
Eric J. Magnusson - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1316

US Classification:

365218

Abstract:

A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.

US Patent:

55441190, Aug 6, 1996

Filed:

Sep 6, 1995

Appl. No.:

8/522980

Inventors:

Steven E. Wells - Citrus Heights CA
Eric J. Magnusson - Orangevale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1700
H01L 2710

US Classification:

36518511

Abstract:

A method for insuring that an erase operation practiced on a block of flash EEPROM transistors is carried out reliably including the steps of: writing whenever the erasure of a block of the flash EEPROM array is to commence to a position in the array to indicate that an erasure of the block has commenced, writing whenever the erasure of a block of the flash EEPROM array is complete to the position in the array to indicate that an erasure of the block has been completed, testing to determine any positions in the array which indicate that an erasure of a block has commenced but not been completed upon applying power to the flash EEPROM array, and reinitiating an erase if any positions in the array exist which indicate that an erasure of a block has commenced but not been completed.