Eric J Schroeder

US Patent:

8539210, Sep 17, 2013

Filed:

Jun 27, 2008

Appl. No.:

12/147746

Inventors:

Joseph Julicher - Maricopa AZ, US
Zacharias Marthinus Smit - Chandler AZ, US
Sean Steedman - Phoenix AZ, US
Vivien Delport - Chandler AZ, US
Jerrold S. Zdenek - Maricopa AZ, US
Ryan Scott Ellison - Chandler AZ, US
Eric Schroeder - Pickerington OH, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 9/48

US Classification:

712228

Abstract:

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

US Patent:

7996651, Aug 9, 2011

Filed:

Jun 27, 2008

Appl. No.:

12/147647

Inventors:

Joseph Julicher - Maricopa AZ, US
Zacharias Marthinus Smit - Chandler AZ, US
Sean Steedman - Phoenix AZ, US
Vivien Delport - Chandler AZ, US
Jerrold S. Zdenek - Maricopa AZ, US
Ryan Scott Ellison - Chandler AZ, US
Eric Schroeder - Gahanna OH, US

Assignee:

Microchip Technology Incorporated - Chandler AZ

International Classification:

G06F 9/35

US Classification:

711220

Abstract:

An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

US Patent:

20080273391, Nov 6, 2008

Filed:

Apr 14, 2008

Appl. No.:

12/102400

Inventors:

Sean Steedman - Phoenix AZ, US
Vivien Delport - Chandler AZ, US
Jerrold S. Zdenek - Maricopa AZ, US
Ruan Lourens - Volente TX, US
Michael Charles - Gilbert AZ, US
Joseph Julicher - Maricopa AZ, US
Eric Schroeder - Gahanna OH, US

International Classification:

G11C 5/14
G11C 11/34

US Classification:

36518518, 365226, 36518533, 365227

Abstract:

An internal voltage regulator in an integrated circuit device is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator protects the low voltage core logic circuits of the integrated circuit device from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory may be part of and operational with the low voltage core logic circuits for storing device operating parameters. Therefore, the internal voltage regulator also protects the low voltage nonvolatile memory from excessive high voltages. Once the integrated circuit device has stabilized and all logic circuits therein are fully function, a bit(s) in the nonvolatile memory may be read to determine if the internal voltage regulator should remain active, e.g., how power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device is powered by a low voltage.

US Patent:

20140019991, Jan 16, 2014

Filed:

Sep 16, 2013

Appl. No.:

14/028458

Inventors:

Zacharias Marthinus Smit - Chandler AZ, US
Sean Steedman - Phoenix AZ, US
Vivien Delport - Chandler AZ, US
Jerrold S. Zdenek - Maricopa AZ, US
Ryan Scott Ellison - Chandler AZ, US
Eric Schroeder - Pickerington OH, US

International Classification:

G06F 9/46

US Classification:

718108

Abstract:

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.