Eric T Stubbs

US Patent:

6335888, Jan 1, 2002

Filed:

Dec 11, 2000

Appl. No.:

09/735120

Inventors:

Kurt D. Beigel - Boise ID
Douglas J. Cutter - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 365207

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6353564, Mar 5, 2002

Filed:

Dec 11, 2000

Appl. No.:

09/735157

Inventors:

Kurt D. Beigel - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

365201, 365203, 36518909

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6388480, May 14, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649192

Inventors:

Eric T. Stubbs - Boise ID
James E. Miller - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03L 706

US Classification:

327156, 327159, 327161, 327263, 327276, 331 17

Abstract:

A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.

US Patent:

6418071, Jul 9, 2002

Filed:

Dec 11, 2000

Appl. No.:

09/735329

Inventors:

Kurt D. Beigel - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 365205

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6445629, Sep 3, 2002

Filed:

Dec 11, 2000

Appl. No.:

09/735330

Inventors:

Kurt D. Beigel - Boise ID
Douglas J. Cutter - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 365203, 365205

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6452846, Sep 17, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/733434

Inventors:

Kurt D. Beigel - Boise ID
Douglas J. Cutter - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 36518911

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6469944, Oct 22, 2002

Filed:

Dec 11, 2000

Appl. No.:

09/735119

Inventors:

Kurt D. Beigel - Boise ID
Manny K. Ma - Boise ID
Gordon D. Roberts - Meridian ID
James E. Miller - Boise ID
Daryl L. Habersetzer - Boise ID
Jeffrey D. Bruce - Meridian ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365201, 365203, 365205

Abstract:

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amps voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amps ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

US Patent:

6570258, May 27, 2003

Filed:

Jun 18, 2001

Appl. No.:

09/884630

Inventors:

Kin F. Ma - Boise ID
Eric T. Stubbs - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2940

US Classification:

257774, 257208, 257758, 257773, 257776, 257907

Abstract:

An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

Address:

4999 E Sagewood Dr, Boise, ID 83716

Phone:

(208)3448049

VIN:

4T1BB46K17U014992

Make:

TOYOTA

Model:

CAMRY HYBRID

Year:

2007