Eric W Swanson

US Patent:

6356872, Mar 12, 2002

Filed:

Sep 25, 1996

Appl. No.:

08/719986

Inventors:

Ka Yin Leung - Austin TX
Eric J. Swanson - Buda TX
Kafai Leung - Austin TX

Assignee:

Crystal Semiconductor Corporation - Austin TX

International Classification:

G10L 2100

US Classification:

704503, 704229

Abstract:

A data conversion device is provided for storing digital data in a DAT ( ) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT ( ) with a noise-shaping filter ( ). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT ( ). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

US Patent:

6369738, Apr 9, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/404667

Inventors:

Eric Swanson - Buda TX 78610

International Classification:

H03M 112

US Classification:

341155, 341118, 341161, 341165, 341114, 341159, 341156, 702 66, 702 74, 702 76, 702 77

Abstract:

A time domain data converter with output frequency domain conversion. A data conversion circuit is operable to receive a signal in the time domain and provide an output in the frequency domain. It includes a data converter for converting data from an analog format to a digital format in the time domain. It also includes a processor for processing the data in the digital format output from the data converter through a time domain/frequency domain transform to provide data in the digital format in the frequency domain. The output of the frequency domain operation or the time domain operation can be provided for output in response to the generation of a data ready signal.

US Patent:

6369740, Apr 9, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/429001

Inventors:

Eric J. Swanson - Buda TX 78610

International Classification:

H03M 112

US Classification:

341155, 341118, 341143

Abstract:

A programmable gain preamplifier is provided which has a low temperature drift and good dynamic range characteristics. The programmable gain preamplifier may be coupled to an analog to digital converter. The analog to digital converter may be a switched capacitor array analog to digital converter. The analog to digital converter may be a resistor array and capacitor array analog to digital converter. A resistor string having contacts out of the resistor string current path may be utilized with the programmable gain preamplifier or the analog to digital converter or both. The resistor string may be utilized to calibrate the analog to digital converter or the programmable gain preamplifier or both. The resistor string may also be utilized by the analog to digital converter when conversions are being performed. The programmable gain preamplifier provides a programmable gain of the difference between two input signals (Ain and Ainâ for example).

US Patent:

6392580, May 21, 2002

Filed:

Jun 11, 1999

Appl. No.:

09/330069

Inventors:

Eric J. Swanson - Buda TX

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03M 112

US Classification:

341155, 607 2

Abstract:

Techniques are disclosed for permitting low power operation of a signal processing circuit, such as a mixed signal processing circuit, by operating devices of the digital signal processing side at an energy-delay minimum. To permit this to occur, the negative logic supply rail of the digital signal processing circuit is operated at a negative potential. This negative potential is generated using a charge pump on an integrated circuit chip which can be also used to create a negative substrate potential. A positive logic supply rail can be generated using a DC to DC converter or voltage regulator. The potential of the positive logic supply rail can be negative, as long at it is more positive than the potential of the negative logic supply rail.

US Patent:

6414619, Jul 2, 2002

Filed:

Sep 4, 2001

Appl. No.:

09/945926

Inventors:

Eric J. Swanson - Buda TX 78610

International Classification:

H03M 112

US Classification:

341155, 341139

Abstract:

An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

US Patent:

6445791, Sep 3, 2002

Filed:

Aug 9, 1999

Appl. No.:

09/370404

Inventors:

Robert Thomas Grisamore - Austin TX
Kartika Putra Prihadi - Austin TX
Eric Swanson - Buda TX
Karl Nordling - Raleigh NC
Axel Thomsen - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

H04M 100

US Classification:

379402, 379403, 379404, 379405, 37939004, 379391, 379392, 37939901, 379 9305, 37940601, 37940607

Abstract:

An interface for coupling a modem port with a transmission line includes a hybrid converter having a variable gain amplifier coupling a transmit path of a first differential polarity and a received path of a second differential polarity.

US Patent:

6452519, Sep 17, 2002

Filed:

Nov 2, 1999

Appl. No.:

09/432502

Inventors:

Eric J. Swanson - Buda TX

Assignee:

Silicon Laboratories, Inc. - Austin TX

International Classification:

H03M 110

US Classification:

341120, 341155

Abstract:

A successive approximation ADC is provided. Contacts to a resistor string may be placed outside of the current path of the resistor string to provide a highly stable resistor string having a very low temperature drift. The resistor string may be utilized to calibrate a successive approximation ADC. The resistor string may also be a portion of a resistor array of a resistor and capacitor array ADC. The resistor string may be calibrated with a calibration ADC having a resolution greater than the resistor string. The calibration ADC may be a delta sigma ADC.

US Patent:

6590517, Jul 8, 2003

Filed:

Feb 1, 2002

Appl. No.:

10/061791

Inventors:

Eric J. Swanson - Buda TX 78610

International Classification:

H03M 112

US Classification:

341155, 341139

Abstract:

An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis. The conversion system may also include the use of a backup conversion path for use when the main conversion path overranges. The backup conversion path may utilize a dedicated backup converter. The backup conversion path may alternatively utilize the estimation converter to generate backup conversions or may utilize the main converter to generate backup conversions.