Erik C Swanson

US Patent:

20050237126, Oct 27, 2005

Filed:

Apr 27, 2004

Appl. No.:

10/832677

Inventors:

Samuel Babb - Fort Collins CO, US
Erik Swanson - Fort Collins CO, US
Lowell Kolb - Loveland CO, US

International Classification:

H01P005/02

US Classification:

333034000

Abstract:

A printed wiring board comprises a first plane having a split formed therein and at least one signal trace disposed on a second plane. The signal trace comprises an increased width in an area of the second plane corresponding to a location of the split.

US Patent:

20060255878, Nov 16, 2006

Filed:

Jul 20, 2006

Appl. No.:

11/489980

Inventors:

Samuel Babb - Fort Collins CO, US
Erik Swanson - Fort Collins CO, US
Lowell Kolb - Loveland CO, US

International Classification:

H03H 7/38

US Classification:

333033000

Abstract:

A printed wiring board comprises a first plane having a split formed therein and at least one signal trace disposed on a second plane. The signal trace comprises an increased width in an area of the second plane corresponding to a location of the split.

US Patent:

20220175089, Jun 9, 2022

Filed:

Dec 3, 2021

Appl. No.:

17/542130

Inventors:

- Denver CO, US
Randon Kruse - Denver CO, US
Eric Irwin - Denver CO, US
Daniel Hipwood - Englewood CO, US
Mark Clementi - Denver CO, US
Brendan Hoskens - Denver CO, US
Erik Suomi - Denver CO, US
Charles Clay Corbett - Denver CO, US
Geoff Gloceri - Denver CO, US
Ryan Wesson - Denver CO, US
Eric Whewell - Denver CO, US
Jeffrey Gay - Denver CO, US
Taylor James DiTallo - Denver CO, US
Cody Henderson - Denver CO, US
Erik Anders Swanson - Denver CO, US

Assignee:

Boa Technology Inc. - Denver CO

International Classification:

A43C 1/06
A43B 5/04

Abstract:

A boot, such as a ski boot, may include a lower portion or shell that is configured to accommodate a foot and an upper portion or cuff that extends upward from the lower portion and that is configured to accommodate a lower leg of a wearer. The boot may also include a tightening system that is coupled with the lower portion of the boot in order to close and tighten the lower portion about the foot. The tightening system includes a reel based closure device and a tension member that is operably coupled with the reel based closure device so that an operation of the reel based closure device effects tensioning of the tension member. The tightening system also includes a plurality of guide members that route or direct the tension member along a path and a terminal member that is fixedly coupled with the tension member.

US Patent:

20230034072, Feb 2, 2023

Filed:

Jul 30, 2021

Appl. No.:

17/389838

Inventors:

- Santa Clara CA, US
Erik Swanson - Fort Collins CO, US
Eric Dixon - Fort Collins CO, US
Todd Baumgartner - Fort Collins CO, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

US Patent:

20230034933, Feb 2, 2023

Filed:

Jul 30, 2021

Appl. No.:

17/390149

Inventors:

- Santa Clara CA, US
Erik Swanson - Fort Collins CO, US
Eric Dixon - Fort Collins CO, US

International Classification:

G06F 9/48
G06F 9/38

Abstract:

Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

US Patent:

20210132985, May 6, 2021

Filed:

Oct 30, 2019

Appl. No.:

16/668469

Inventors:

- Santa Clara CA, US
Erik SWANSON - Fort Collins CO, US

International Classification:

G06F 9/48
G06F 9/30

Abstract:

A processing system includes a processor core and a scheduler coupled to the processor core. The processing system executes a first active thread and a second active thread in the processor core and detects a swap event for the first active thread or the second active thread. Based on the swap event, using a shadow-latch configured fixed mapping system, to the processing system replaces either the first active thread or the second active thread with a shadow-based thread, the shadow-based thread being stored in a shadow-latch configured register file.

US Patent:

20210117196, Apr 22, 2021

Filed:

Oct 22, 2019

Appl. No.:

16/660495

Inventors:

- Santa Clara CA, US
- Markham, CA
Erik SWANSON - Fort Collins CO, US
Sneha V. DESAI - Markham, CA
Donglin JI - Fort Collins CO, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.

US Patent:

20210096857, Apr 1, 2021

Filed:

Sep 27, 2019

Appl. No.:

16/585973

Inventors:

- Santa Clara CA, US
Scott Thomas BINGHAM - Santa Clara CA, US
John M. KING - Austin TX, US
Michael ESTLICK - Fort Collins CO, US
Erik SWANSON - Fort Collins CO, US
Robert WEIDNER - Fort Collins CO, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.