Ernest P Khaw

US Patent:

6515503, Feb 4, 2003

Filed:

Apr 1, 2002

Appl. No.:

10/113485

Inventors:

Jed Griffin - Forest Grove OR
Ernest Khaw - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 30, 326 27, 326 83, 327112

Abstract:

A circuit is presented having many transistors connected in parallel between a supply node and a pre-drive stage. The many transistors each have a gate connected to a delay select line to control current through the pre-drive stage. Also presented is a circuit having a first stack of transistors connected between a first supply node and a pre-drive stage. The circuit also has a second stack of transistors connected between a second supply node and the pre-drive stage, and many delay select lines. The stack of transistors each have a gate connected to one of the delay select lines.

US Patent:

6601196, Jul 29, 2003

Filed:

Jun 29, 2000

Appl. No.:

09/608449

Inventors:

Sanjay Dabral - Palo Alto CA
Ramesh Senthinathan - Folsom CA
Ming Zeng - San Jose CA
Keith Self - Aloha CA
Ernest Khaw - Beaverton OR
Chung-Wai Yue - Worchester MA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 43

Abstract:

An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.

US Patent:

6400176, Jun 4, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/476425

Inventors:

Jed Griffin - Forest Grove OR
Ernest Khaw - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 30, 326 86, 327108

Abstract:

According to one aspect of the invention, a circuit is provided that includes a drive stage having an input and output node, and at least one transistor coupled between the two nodes. An upper impedance element coupled at one end to the output node and at another end to an upper supply node is provided. The upper impedance element has a stack of transistors each having a beta matched to a beta of at least one transistor in the drive stage. A lower impedance element coupled at one end to the output node and at another end to a lower supply node is provided. The lower impedance element has a stack of transistors each having a beta matched to the beta of at least one transistor in the drive stage. In another embodiment, a circuit is provided that includes a plurality of transistors coupled in parallel between a supply node and a pre-drive stage. The plurality of transistors each have a gate coupled to a delay select line to control current through the pre-drive stage.