Eugene D Smith

US Patent:

6857938, Feb 22, 2005

Filed:

Dec 16, 2002

Appl. No.:

10/320012

Inventors:

Eugene C. Smith - Apple Valley MN, US
Russell J. Elias - Tempe AZ, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

B24B049/00
B24B051/00
B24B001/00
B24B005/00

US Classification:

451 5, 451 41, 451287

Abstract:

One embodiment disclosed relates to a chemical-mechanical polishing process. The process includes performing chemical-mechanical polishing on an entire wafer lot without look ahead polishing of a first article wafer. A normalized polish rate is determined, and a process time for a next wafer lot is predicted using the normalized polish rate. Another embodiment of the invention relates to a polishing apparatus for chemical-mechanical planarization of semiconductor wafers.

US Patent:

20030087532, May 8, 2003

Filed:

Nov 1, 2001

Appl. No.:

10/001933

Inventors:

Biao Wu - Cupertino CA, US
Erik Olson - Shakopee MN, US
Ramkumar Krishnaswamy - San Jose CA, US
Eugene Smith - Apple Valley MN, US

International Classification:

H01L021/311
H01L021/302
H01L021/461

US Classification:

438/745000

Abstract:

The present invention provides integrated systems and methods for carrying out manufacturing steps relating to etching, photoresist stripping and optionally, particle removal. More specifically, the present invention provides integrated systems and methods which may be utilized to etch oxide with subsequent removal of photoresist using BOE solutions that are desirably blended on-line. Advantageously, systems and methods embodying features of the present invention include a single process chamber so that cycle time and individual step processing time are reduced, further resulting in increased productivity of the systems and methods.

US Patent:

62551809, Jul 3, 2001

Filed:

May 1, 2000

Appl. No.:

9/565292

Inventors:

Eugene C. Smith - Apple Valley MN

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H01L 21336

US Classification:

438301

Abstract:

The present invention advantageously provides a method for forming a nitride sidewall spacer having a relatively thin upper portion and a lower portion that increases in lateral thickness as it substantially tapers toward an underlying surface. In an embodiment, nitride sidewall spacers having this shape are formed upon the opposed sidewall surfaces of gate conductors which are dielectrically spaced above a semiconductor substrate. The upper portion of each spacer is bounded by a substantially vertical upper outer surface while the lower portion is bounded by a lower outer surface which is angled away from the upper outer surface. A unitary source/drain implant may be forwarded into the substrate to form graded junctions. The implant is self-aligned to the upper outer surfaces of the nitride spacers. As such, the graded junctions are displaced laterally from the gate conductors by a distance which is dictated by the lateral thickness of the upper portion of each spacer.

US Patent:

62217763, Apr 24, 2001

Filed:

May 5, 1998

Appl. No.:

9/073033

Inventors:

Eugene C. Smith - Apple Valley MN

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 2100

US Classification:

438692

Abstract:

The present invention advantageously provides a method and apparatus in which a sacrificial anti-reflective coating is used as an etch stop layer to protect a material from being etched. The anti-reflective coating has a relatively high viscosity which allows it to pool in recess regions as it is spin-on deposited across a surface having elevational disparities. This feature of the anti-reflective coating may be taken advantage of when using the anti-reflective coating as an etch stop layer. That is, the anti-reflective coating may be spin-on deposited across a substrate and structures arranged upon the substrate to allow the anti-reflective coating to accumulate in the recess regions interposed between the structures. In this manner, a thicker layer of the anti-reflective coating is formed in the recessed region above the substrate than above the structures which comprises a first layer of material arranged upon a second layer of material. Thus, an etch chemistry which exhibits a relatively high selectivity ratio of the first layer of material relative to the anti-reflective coating may be used to etch the relatively thin layer of the anti-reflective coating and the first layer of material from above the second layer of material.