Eugene E Weber

US Patent:

7313713, Dec 25, 2007

Filed:

Aug 20, 2004

Appl. No.:

10/923403

Inventors:

Eugene F. Weber - Emmaus PA, US
Matthew R. Henry - Fogelsville PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 1/32

US Classification:

713324, 713323

Abstract:

A method and apparatus for powering digital logic circuits that provides low power consumption while maintaining high performance. The circuit is divided into logic elements necessary for maintaining the state of the circuit and those that are not. The state-maintaining logic uses low-leakage, low performance transistors, and is continually powered. The remainder of the circuit uses standard transistors, i. e. , high performance, high-leakage transistors, and is only powered when the circuit is active, i. e. , not in a standby mode. Two power rails are used, one for the state maintaining components and one for the non-state-maintaining components. The state-maintaining logic is functionally separated from the remainder of the circuit when the remainder of the circuit is being powered up or down to avoid short-circuiting any elements. Typical state-maintaining components are sequential logic gates. Typical non-state maintaining components are combinational logic gates.