Fang Yu

US Patent:

20180285290, Oct 4, 2018

Filed:

Mar 30, 2018

Appl. No.:

15/942065

Inventors:

- Plano TX, US
Alan Gatherer - Richardson TX, US
Xi Chen - Plano TX, US
Fang Yu - San Jose CA, US
Yichuan Yu - Shanghai, CN
Bin Yang - Shanghai, CN
Wei Chen - Shanghai, CN

Assignee:

Futurewei Technologies, Inc. - Plano TX

International Classification:

G06F 13/16
G06F 13/40
G06F 13/42

Abstract:

A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

US Patent:

20170293512, Oct 12, 2017

Filed:

Apr 12, 2016

Appl. No.:

15/096966

Inventors:

- Plano TX, US
Alan Gatherer - Richardson TX, US
Alex Elisa Chandra - Plano TX, US
Lee Dobson Mcfearin - Plano TX, US
Mark Brown - Little Elm TX, US
Debashis Bhattacharya - Plano TX, US
Fang Yu - San Jose CA, US
Xingfeng Chen - Shanghai, CN
Yan Bei - Shanghai, CN
Ke Ning - Shenzhen, CN
Chushun Huang - Shenzhen, CN
Tong Sun - Allen TX, US
Xiaotao Chen - Basking Ridge NJ, US

International Classification:

G06F 9/54
G06F 13/28

Abstract:

Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

US Patent:

20170293586, Oct 12, 2017

Filed:

Apr 12, 2016

Appl. No.:

15/097091

Inventors:

- Plano TX, US
Alex Elisa Chandra - Plano TX, US
Lee Dobson McFearin - Plano TX, US
Fang Yu - San Jose CA, US
Alan Gatherer - Richardson TX, US

International Classification:

G06F 13/42
G06F 13/20
G06F 15/78

Abstract:

Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m−k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

US Patent:

20170293587, Oct 12, 2017

Filed:

Apr 12, 2016

Appl. No.:

15/096982

Inventors:

- Plano TX, US
Alex Elisa Chandra - Plano TX, US
Xiaotao Chen - Basking Ridge NJ, US
Alan Gatherer - Richardson TX, US
Fang Yu - San Jose CA, US
Xingfeng Chen - Shanghai, CN
Zhuolei Wang - Shanghai, CN
Yang Zhou - Shanghai, CN

International Classification:

G06F 13/42
G06F 13/40

Abstract:

A described embodiment of the present invention includes a network having a first, second an d third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.