Fen Yi Chen

US Patent:

8405135, Mar 26, 2013

Filed:

Oct 5, 2010

Appl. No.:

12/898340

Inventors:

Chih-Chao Yang - Glenmont NY, US
Fen Chen - Williston VT, US
Baozhen Li - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/108

US Classification:

257301, 257E21396, 257E27092, 438386, 438387

Abstract:

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.