Feng Shi L Chen

US Patent:

6433711, Aug 13, 2002

Filed:

Nov 9, 2000

Appl. No.:

09/711349

Inventors:

Feng Chen - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 106

US Classification:

341118, 341172, 341156

Abstract:

An offset error compensation system is provided that includes a comparator ( ) having an offset error ( ), a positive receptor ( ), a negative receptor ( ), a positive output ( ), and a negative output ( ). A sequence generator ( ) generates control signals (22) representing normal cycles and swap cycles. A first cross connect ( ) is coupled to the positive receptor ( ), the negative receptor ( ), a positive input signal ( ), and a negative input signal ( ). The first cross connect ( ) couples the positive input signal ( ) to the positive receptor ( ) and the negative input signal ( ) to the negative receptor ( ) in response to a normal cycle. The first cross connect ( ) further couples the positive input signal ( ) to the negative receptor ( ) and the negative input signal ( ) to the positive receptor ( ) in response to a swap cycle. A second cross connect ( ) is coupled to the positive receptor ( ), the negative receptor ( ), the positive output ( ), and the negative output ( ). The second cross connect ( ) couples the positive receptor ( ) to the positive output ( ) and the negative receptor ( ) to the negative output ( ) in response to the normal cycle.

US Patent:

6697003, Feb 24, 2004

Filed:

Apr 17, 2003

Appl. No.:

10/417616

Inventors:

Feng Chen - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 300

US Classification:

341143, 341144, 341155

Abstract:

Dynamic element matching systems and methods are provided in which a current dynamic element matching code is generated according to a previous dynamic element matching code, a digital input code, and a dither code. The current dynamic element matching code is then used along with the digital input code to select digital to analog converter elements.

US Patent:

6897701, May 24, 2005

Filed:

May 13, 2003

Appl. No.:

10/436769

Inventors:

Feng Chen - Plano TX, US
Donald C. Richardson - Plano TX, US
Christopher L. Betty - Arlington TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L005/00

US Classification:

327307, 327530

Abstract:

A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (V(V)) and nonlinear junction capacitance (C(V)) can be substantially removed.

US Patent:

6914549, Jul 5, 2005

Filed:

Sep 12, 2003

Appl. No.:

10/661861

Inventors:

Feng Chen - Plano TX, US
Ranjit Gharpurey - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M001/12

US Classification:

341155, 341143

Abstract:

Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

US Patent:

7006023, Feb 28, 2006

Filed:

Sep 12, 2003

Appl. No.:

10/661019

Inventors:

Feng Chen - Plano TX, US

Assignee:

Texas Instruments Inc. - Dallas TX

International Classification:

H03M 3/00

US Classification:

341143, 341155

Abstract:

Digitizing a signal includes sampling and holding an analog signal to yield a sampled signal, where the analog signal includes information. The sampled signal is filtered at a passive filter circuit to yield a filtered signal. The passive filter circuit includes at least one passive element and the filtered signal is characterized by a bandpass response. The filtered signal is quantized to yield a digital signal, where the digital signal corresponds to the analog signal and the digital signal includes the information.

US Patent:

7030792, Apr 18, 2006

Filed:

Sep 28, 2005

Appl. No.:

11/237250

Inventors:

Feng Chen - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 1/06
H03M 3/00
G06F 15/00
G06F 7/00

US Classification:

341118, 341143, 708209

Abstract:

A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC ( and/or ) that is part of a modulator (FIG. ). A low pass averaging (LPA) index decoder controls a shifting arrangement to shift a digital word T derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. ). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder causes the shifting arrangement to shift the digital word T using only a single pointer per clock cycle.

US Patent:

7053808, May 30, 2006

Filed:

Nov 26, 2003

Appl. No.:

10/723472

Inventors:

Feng Chen - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 1/66
H03M 1/06

US Classification:

341144, 341118

Abstract:

A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC ( and/or ) that is part of a modulator (FIG. ). A low pass averaging (LPA) index decoder controls a shifting arrangement to shift a digital word T derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. ). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder causes the shifting arrangement to shift the digital word T using only a single pointer per clock cycle.

US Patent:

7057540, Jun 6, 2006

Filed:

Oct 17, 2002

Appl. No.:

10/273217

Inventors:

Khurram Muhammad - Dallas TX, US
Robert B. Staszewski - Garland TX, US
Feng Chen - Plano TX, US
Dirk Leipold - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 3/00

US Classification:

341143, 341155

Abstract:

A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer with such a sampling circuit. The present invention discloses a sampling circuit using switched capacitors , and with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.