Feng Gao

US Patent:

20170032846, Feb 2, 2017

Filed:

Aug 26, 2016

Appl. No.:

15/249306

Inventors:

- San Jose CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
Dana Lee - Santa Clara CA, US

International Classification:

G11C 16/34
G11C 16/26
G11C 16/14
G11C 16/10
G11C 16/04

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

US Patent:

20140340967, Nov 20, 2014

Filed:

Jun 27, 2014

Appl. No.:

14/318502

Inventors:

- San Jose CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
Dana Lee - Santa Clara CA, US

International Classification:

G11C 16/10
G11C 16/14

US Classification:

36518529, 36518518

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.