Fethi M Dhaoui

US Patent:

7285818, Oct 23, 2007

Filed:

Jun 15, 2005

Appl. No.:

11/155005

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7342278, Mar 11, 2008

Filed:

May 18, 2007

Appl. No.:

11/750650

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7368789, May 6, 2008

Filed:

Jun 13, 2005

Appl. No.:

11/152018

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Frank Hawley - Campbell CA, US
Leslie Richard Wilkinson - Cave Junction OR, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/76

US Classification:

257369, 257314

Abstract:

A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

US Patent:

7430137, Sep 30, 2008

Filed:

Oct 8, 2007

Appl. No.:

11/868694

Inventors:

Jonathan W. Greene - Palo Alto CA, US
Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/02
G11C 5/02
G11C 5/06
G06F 7/38
H03K 19/173
H03K 19/177
H03K 19/94

US Classification:

36518505, 365188, 36518902, 36523002, 326 38, 326 39, 326 44, 326 49

Abstract:

A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.

US Patent:

7473960, Jan 6, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/927265

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - San Jose CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7501681, Mar 10, 2009

Filed:

Dec 21, 2007

Appl. No.:

11/962615

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7522453, Apr 21, 2009

Filed:

Dec 20, 2007

Appl. No.:

11/961134

Inventors:

Zhigang Wang - Sunnyvale CA, US
Gregory Bakker - San Jose CA, US
Volker Hecht - Barshinghausen, DE
Santosh Yachareni - San Jose CA, US
Fethi Dhaoui - Patterson CA, US
Vidyadhara Bellippady - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/04

US Classification:

36518511, 36518513, 36518517

Abstract:

A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.

US Patent:

7538379, May 26, 2009

Filed:

Dec 16, 2005

Appl. No.:

11/303865

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.