Frances D Koo

US Patent:

47422939, May 3, 1988

Filed:

Apr 6, 1987

Appl. No.:

7/034973

Inventors:

Frances D. Koo - Los Angeles CA
Gene W. Lee - Huntington Beach CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

G01R 3128

US Classification:

324 73R

Abstract:

A method and apparatus are disclosed for testing for stuck- open faults in integrated circuits (10) having a plurality of combinational logic devices (18, 20). The apparatus includes a chain of shift register stages (22), with each stage including at least two latches (L1 and L3). The bits of an initialization test are shifted down the shift register and loaded into one of the latches (L3), while the bits of a detection test pattern are subsequently shifted down the chain and stored in the other latch (L1). A multiplexer (50) is provided for selecting one of the outputs from the two latches (L1, L3) so that the initialization test pattern and then the detection test pattern can be quickly applied to the combinational logic so as to minimize hazards which could invalidate the test results.

US Patent:

48336769, May 23, 1989

Filed:

Jul 30, 1987

Appl. No.:

7/079372

Inventors:

Frances D. Koo - Los Angeles CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

G01R 3128

US Classification:

371 15

Abstract:

A method and apparatus are disclosed for testing for stuck open faults in integrated circuits (10) having a plurality of combinational logic devices (18, 20). The apparatus includes a chain or shift register stages (22), with each stage including at lest two latches (L1and L2). Provision (43) is made for interleaving the bits of an initialization test pattern (40) with the bits of a detection test pattern (42) prior to loading the resultant serial data stream into the shift register stages (22). Once loaded, the latches (L2) contain the initialization test pattern whereas the latches (L1) hold the detection test pattern. A multiplexer (52) is provided for selecting one of the outputs from the two latches (L1, L2) so that the initialization test pattern and then the detection test pattern can be quickly applied to the combinational logic so as to minimize hazards which could invalidate the test results.