Frank D Ferraiolo

US Patent:

6421784, Jul 16, 2002

Filed:

Mar 5, 1999

Appl. No.:

09/263671

Inventors:

Albert Manhee Chu - Essex VT
Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Kevin Charles Gower - LaGrangeville NY
Roger Paul Gregor - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 112

US Classification:

713401, 327276

Abstract:

A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.

US Patent:

6442223, Aug 27, 2002

Filed:

Apr 26, 1999

Appl. No.:

09/299716

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Kevin Charles Gower - LaGrangeville NY
Toru Kobayashi - Saitama, JP
Bradley David McCredie - Austin TX
Hideo Sawamoto - Asahimachi, JP

Assignee:

International Business Machines Corporation - Armonk NY
Hitachi, Ltd. - Tokyo

International Classification:

H04L 700

US Classification:

375354

Abstract:

A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register, the data is accessible at the data sink at a controllable predetermined time.

US Patent:

6470458, Oct 22, 2002

Filed:

Jul 29, 1999

Appl. No.:

09/363951

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Daniel John Kolor - Wappingers Falls NY
Bradley McCredie - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 112

US Classification:

713400, 713 1, 713500, 713600

Abstract:

A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chips clock phase as a reference clock phase for the secondary chips.

US Patent:

6542999, Apr 1, 2003

Filed:

Nov 5, 1999

Appl. No.:

09/434801

Inventors:

Daniel Mark Dreps - Georgetown TX
Kevin Charles Gower - LaGrangeville NY
Frank David Ferraiolo - Essex VT

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 112

US Classification:

713400, 710 20

Abstract:

An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

US Patent:

6546530, Apr 8, 2003

Filed:

Sep 14, 2000

Appl. No.:

09/662417

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex Junction VT
Jing Fang Hao - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6, 327278

Abstract:

A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.

US Patent:

6571346, May 27, 2003

Filed:

Nov 5, 1999

Appl. No.:

09/434800

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Kevin Charles Gower - LaGrangeville NY
Bradley McCredie - Austin TX
Paul Coteus - Yorktown NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 104

US Classification:

713600, 713500

Abstract:

A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (âBus clockâ) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (âLocal clockâ) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master. The data sets are read in their respective sequence from the latches, responsive to the Local clock, so that the holding of respective data sets for the relatively longer time intervals in multiple latches and the reading of the data in sequence increases allowable skew of the Local clock relative to the received Bus clock.

US Patent:

6654897, Nov 25, 2003

Filed:

Mar 5, 1999

Appl. No.:

09/263662

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Kevin Charles Gower - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 112

US Classification:

713401, 713400, 713500, 713502, 713503, 713600

Abstract:

An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

US Patent:

6671753, Dec 30, 2003

Filed:

Sep 24, 2001

Appl. No.:

09/961506

Inventors:

Daniel Mark Dreps - Georgetown TX
Frank David Ferraiolo - Essex VT
Kevin Charles Gower - LaGrangeville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710 60, 710305

Abstract:

An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.