Frank H Peters

US Patent:

6341137, Jan 22, 2002

Filed:

Apr 27, 1999

Appl. No.:

09/300252

Inventors:

Vijaysekhar Jayaraman - Goleta CA
Jonathan Geske - Lompoc CA
Frank Peters - Lompoc CA

Assignee:

Gore Enterprise Holdings, Inc. - Newark DE

International Classification:

H01S 500

US Classification:

372 50, 372 23

Abstract:

A semiconductor device includes an array of long-wavelength VCSELs pumped by a short-wavelength optical pump. The array of long-wavelength VCSELs includes a series of semiconductor recesses, where each semiconductor recess is between two layers of a VCSEL, substantially overlapping the transverse model profile of the VCSEL under operation.

US Patent:

6341138, Jan 22, 2002

Filed:

Jun 16, 1999

Appl. No.:

09/334590

Inventors:

Frank Peters - Lompoc CA
Michael H. MacDougal - Goleta CA

Assignee:

Gore Enterprise Holdings, Inc. - Newark DE

International Classification:

H01S 308

US Classification:

372 96

Abstract:

Diode lasers are fabricated whose performance is essentially unchanged over designed temperature and bias ranges. The threshold current (I ) and the external efficiency ( ) of the diode lasers are unchanged over a range of specified temperatures.

US Patent:

6465811, Oct 15, 2002

Filed:

Jul 12, 1999

Appl. No.:

09/351702

Inventors:

Frank Peters - Lompoc CA
Jonathan Geske - Lompoc CA

Assignee:

Gore Enterprise Holdings, Inc. - Newark DE

International Classification:

H01L 2348

US Classification:

257 99, 257773

Abstract:

In a vertical cavity surface emitting laser (VCSEL), the metal contact area, the associated metal bonding pad and the interconnecting metal bridge are deposited on top of a conductive upper mirror stack. To prevent current flow from the pad through the conductive mirror stack which would bypass the active medium, a moat is etched surrounding the pad area. The moat isolates the pad area and the conductive material beneath the pad area. In a method of making a VCSEL, the semiconductor layered portion of an optical semiconductor device is first formed on a suitable substrate. Such semiconductor layers can include various layers of conductive, semiconductive or insulating material as may be required for the type of device being constructed. The metal contact and the metal bonding pad areas together with an interconnecting metal bridge are then deposited on the surface of the semiconductor layers. The structure is then etched down from the top surface to form a moat surrounding the bonding pad area which electrically isolates the semiconductor layered material beneath the bonding pad.

US Patent:

6771682, Aug 3, 2004

Filed:

Oct 30, 2002

Appl. No.:

10/283476

Inventors:

Frank H. Peters - San Jose CA

Assignee:

Infinera Corporation - Sunnyvale CA

International Classification:

H01S 500

US Classification:

372 50, 372 45

Abstract:

Electrical isolation regions are formed between adjacently disposed electro-optical components integrated in a monolithic semiconductor photonic chip, such as an EML or PIC chip. A bias, V , is applied to the isolation region so that any parasitical current path developed between adjacent active or passive optical components, now separated by an isolation region, is established through the electrical isolation region and clamped to the bias, V. The applied bias, V , may be a positive bias, a negative bias, or a zero or a ground bias. The electrical isolation regions are formed by spatial current blocking regions formed at adjacent sides of the electrical isolations region transverse to a direction of light propagation through the optical components, or between the electrical isolation regions and adjacent optical components. The spatial current blocking regions may be comprised of a pair of spatially disposed trenches or ion implanted regions or high resistance implanted regions.

US Patent:

6804271, Oct 12, 2004

Filed:

Nov 6, 2001

Appl. No.:

10/011503

Inventors:

Ken Nishimura - Fremont CA
Scott Corzine - Sunnyvale CA
Frank H. Peters - San Jose CA
Gary Gordon - Saratoga CA

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01S 310

US Classification:

372 27, 372 43, 372 44, 372 45, 372 46, 372 47, 372 48, 372 49, 372 50, 372 99, 372105

Abstract:

Light emission methods and light emission devices are described including method and devices capable of emitting light at a plurality of controllable wavelengths. According to one aspect, a light emission method includes providing a control signal and emitting light using a laser operating in a plurality of polarization states. The polarization state of the laser is adjusted responsive to the control signal and the wavelength of the light emitted using the laser is adjusted responsive to the adjustment of the polarization state of the laser.

US Patent:

6839370, Jan 4, 2005

Filed:

Dec 31, 2001

Appl. No.:

10/040167

Inventors:

Frank H. Peters - San Jose CA, US
Michael H. Leary - Fremont CA, US
Yoon-Kyu Song - San Jose CA, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H01S 500

US Classification:

372 46, 372 45

Abstract:

An optoelectronic device such as a vertical cavity surface emitting laser (VCSEL) includes a tunnel junction that conducts a current of holes tunneling into an active region. Tunneling in a selected area of the tunnel junction is disabled to form a current blocking region that confines the current to desired regions. Tunneling can be disabled in the selected area using techniques including but not limited to implanting or diffusing dopants, disrupting crystal structure, or etching to remove part of the tunnel junction.

US Patent:

6922422, Jul 26, 2005

Filed:

Oct 30, 2002

Appl. No.:

10/283475

Inventors:

Frank H. Peters - San Jose CA, US
Radhakrishnan L. Nagarajan - Cupertino CA, US

International Classification:

H01S003/04

US Classification:

372 36, 372 34, 372 50, 385 14

Abstract:

Photonic integrated circuits (PIC) semiconductor chips are provided with thermal isolation and/or heat dissipation structures between integrated optical components in the PIC chip, particularly integrated active optical components. These structures may also serve as a ground path for electrical circuitry on the PIC chip. An important function is the enhanced thermal isolation from, or dissipation of heat from, between adjacent or neighboring optical components in the PIC so that required spacing between adjacent optical components can be made even less than the thickness of the substrate thereby realizing a more compact optical component array on the monolithic PIC chips.

US Patent:

6999489, Feb 14, 2006

Filed:

Mar 24, 2004

Appl. No.:

10/807729

Inventors:

Frank H. Peters - San Jose CA, US

Assignee:

Infinera Corporation - Sunnyvale CA

International Classification:

H01S 5/00

US Classification:

372 50, 372 45

Abstract:

A method of electrically isolating and operating electro-optical components integrated in a monolithic semiconductor photonic chip, such as an EML or PIC chip. A bias, V, is applied to the isolation region so that any parasitical current path developed between adjacent active or passive optical components, now separated by an isolation region, is established through the electrical isolation region and clamped to the bias, V. The applied bias, V, may be a positive bias, a negative bias, or a zero or a ground bias. The electrical isolation regions are formed by spatial current blocking regions formed at adjacent sides of the electrical isolations region transverse to a direction of light propagation through the optical components, or between the electrical isolation regions and adjacent optical components. The spatial current blocking regions may be comprised of a pair of spatially disposed trenches or ion implanted regions or high resistance implanted regions.