Frank C Verhoorn

US Patent:

20030217185, Nov 20, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/113477

Inventors:

Anshuman Thakur - Beaverton OR, US
Frank Verhoorn - Beaverton OR, US

International Classification:

G06F015/16

US Classification:

709/250000, 710/261000

Abstract:

A system to accumulate routine and critical interrupt-triggering events, and generate an interrupt. A network communicates data. A computing device executes an operating system. A Network Interface Card (NIC) communicates data with the network and with the operating system, and invokes an interrupt. The NIC accumulates routine interrupt-triggering events and includes a timer to limit a length of time during which routine interrupt-triggering events accumulate, and if a critical interrupt-triggering event is received or the timer expires, the interrupt is invoked and the timer is reset. A driver provides an interface between the operating system and the NIC.

US Patent:

56130716, Mar 18, 1997

Filed:

Jul 14, 1995

Appl. No.:

8/502071

Inventors:

Linda J. Rankin - Beaverton OR
Joseph Bonasera - Portland OR
Nitin Y. Borkar - Beaverton OR
Linda C. Ernst - Portland OR
Suvansh K. Kapur - Beaverton OR
Daniel A. Manseau - Portland OR
Frank Verhoorn - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1202

US Classification:

39520016

Abstract:

A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.

US Patent:

59304863, Jul 27, 1999

Filed:

Sep 9, 1996

Appl. No.:

8/707884

Inventors:

Lily Pao Looi - Portland OR
Nitin Borkar - Beaverton OR
Frank Verhoorn - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13362

US Classification:

395293

Abstract:

A computer system includes a priority arbitration scheme that prevents "hogging" of a bus by a priority agent. The computer system comprises at least one agent, at least one priority agent, a system resource, and a bus coupling the agent, priority agent, and system resource to one another. An arbiter is coupled to the bus, agent, and priority agent to receive request signals from the agent and the priority agent and to grant control of the bus to one of the agent and priority agent for access to the system resource. The priority agent is granted control of the bus whenever the priority agent asserts a request signal, as soon as the bus becomes next available. The priority agent relinquishes control of the bus to the agent, for a predetermined portion of the bus bandwidth, when a request signal is asserted by the agent.