Frank I Yu

US Patent:

7333364, Feb 19, 2008

Filed:

Apr 19, 2007

Appl. No.:

11/737336

Inventors:

Frank Yu - Palo Alto CA, US
Charles C. Lee - Cupertino CA, US
Abraham C. Ma - Fremont CA, US
Ming-Shiang Shen - Taipei Hsien, TW

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

G11C 16/06

US Classification:

36518509, 36518522, 36518511

Abstract:

A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

US Patent:

7440287, Oct 21, 2008

Filed:

Oct 11, 2007

Appl. No.:

11/871103

Inventors:

Jim Chin-Nan Ni - San Jose CA, US
David Q. Chow - San Jose CA, US
Frank I-Kang Yu - Palo Alto CA, US
Abraham C. Ma - Fremont CA, US
Ming-Shiang Shen - Taipei, TW

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

H05K 7/02
H05K 7/10

US Classification:

361752, 361730, 361736, 439660, 439951, 439945, 174 5051, 174 5052

Abstract:

An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket.

US Patent:

7440316, Oct 21, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/741890

Inventors:

Charles C. Lee - Cupertino CA, US
Frank I-Kang Yu - Palo Alto CA, US
David Q. Chow - San Jose CA, US

Assignee:

Super Talent Electronics, Inc - San Jose CA

International Classification:

G11C 11/00

US Classification:

365163, 365148

Abstract:

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are un-inverted. Peak currents are thus reduced by encoding to reduce reset data bits.

US Patent:

7471556, Dec 30, 2008

Filed:

May 15, 2007

Appl. No.:

11/748595

Inventors:

David Q. Chow - San Jose CA, US
Charles C. Lee - Cupertino CA, US
Frank I-Kang Yu - Palo Alto CA, US

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

G11C 11/00

US Classification:

365163, 36523003, 36518905

Abstract:

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux.

US Patent:

7475174, Jan 6, 2009

Filed:

Jul 5, 2007

Appl. No.:

11/773827

Inventors:

David Q. Chow - San Jose CA, US
Charles C. Lee - Cupertino CA, US
Frank I-Kang Yu - Palo Alto CA, US

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

G06F 12/00
G06F 3/00
G06F 13/00

US Classification:

710 74, 710 8, 710 9, 710 10, 710 13, 710 72, 710 73, 710313, 711103

Abstract:

A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.

US Patent:

7606111, Oct 20, 2009

Filed:

Jun 27, 2007

Appl. No.:

11/769324

Inventors:

Charles C. Lee - Cupertino CA, US
Frank I-Kang Yu - Palo Alto CA, US
David Q. Chow - San Jose CA, US

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

G11C 7/10

US Classification:

3652385, 365163, 36523003

Abstract:

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

US Patent:

7620769, Nov 17, 2009

Filed:

Feb 13, 2007

Appl. No.:

11/674645

Inventors:

Charles C. Lee - Cupertino CA, US
Frank Yu - Palo Alto CA, US
Abraham C. Ma - Fremont CA, US
Ming-Shiang Shen - Taipei Hsien, TW

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

G06F 12/02

US Classification:

711103, 711156, 711206

Abstract:

A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

US Patent:

7628622, Dec 8, 2009

Filed:

Mar 18, 2008

Appl. No.:

12/050748

Inventors:

Frank I-Kang Yu - Palo Alto CA, US
David Nguyen - San Jose CA, US
Jim Chin-Nan Ni - San Jose CA, US
Abraham C. Ma - Fremont CA, US
Ming-Shiang Shen - Taipei, TW

Assignee:

Super Talent Electronics, Inc. - San Jose CA

International Classification:

H01R 13/44

US Classification:

439131

Abstract:

A portable USB device with an improved configuration is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more multi-level cell (MLC) flash memory devices and an MLC flash controller disposed therein. The portable USB device further includes a housing for enclosing the core unit, including a front end opening to allow the USB plug connector to be deployed. The portable USB device further includes a core unit carrier for carrying the core unit for deploying and retracting the core unit, including a slide button to allow a finger of a user to slide the USB plug connector of the core unit in and out of the housing via the front end opening of the housing.