Fred S Bonn

US Patent:

55510760, Aug 27, 1996

Filed:

Sep 6, 1994

Appl. No.:

8/300768

Inventors:

Fred H. Bonn - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 128

US Classification:

455333

Abstract:

A mixer circuit (10) combines a buffered RF signal with the LO signal at the gate of a mixing transistor (20) for providing sum and difference product terms as the IF output signal. An inductor (46) provides a DC signal path between the source of the mixing transistor and the drain of the buffering transistor (14) to share the same operating current and thereby reduce power consumption in the mixer. The DC path inductor provides a high impedance to block the RF signal and LO signal. A bias circuit (26, 28) sets the bias point at the gate of the mixing transistor to a mid-point value between V. sub. DD and ground potential. In disable mode, the bias point of the mixing transistor is sufficiently low that the LO signal does not have sufficient power to turn on buffering and mixing transistors that could generate mixing products at the IF output.

US Patent:

61602809, Dec 12, 2000

Filed:

Mar 4, 1996

Appl. No.:

8/610504

Inventors:

Fred H. Bonn - Chandler AZ
George B. Norris - Phoenix AZ
John Michael Golio - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2980
H01L 31112

US Classification:

257272

Abstract:

A field effect transistor structure which can serve as a low noise amplifier. The field effect transistor has a major surface and source and drain regions extending from the major surface into a body of semiconductor material. A channel region is formed in a portion of the body of semiconductor material separating the source and drain regions. The channel region has a first boundary perpendicular to the major and contiguous with the source region, a second boundary parallel to the first boundary and contiguous with the drain region, a third boundary perpendicular to the first boundary, and a fourth boundary parallel to the channel region. A first portion of the channel region is enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, a third boundary of the channel region, and the fourth boundary of the channel region. A non-conductive section is formed in the body of semiconductor material extending from the major surface and enclosed by a first edge coinciding with the first border of the first portion of the channel region, a second edged coinciding with the second border of the first portion of the channel region, a third edge parallel to the third boundary of the channel region, and a fourth edge parallel to the fourth boundary of the channel region. A gate structure is formed above the first portion of the channel region.