Frederic C Hayem

US Patent:

6546514, Apr 8, 2003

Filed:

Dec 13, 1999

Appl. No.:

09/460254

Inventors:

Frederic Hayem - San Diego CA
Patrick Arnould - Antibes, FR

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01R 3128

US Classification:

714741, 714726

Abstract:

A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.

US Patent:

7577779, Aug 18, 2009

Filed:

Feb 14, 2006

Appl. No.:

11/353904

Inventors:

Frederic Hayem - San Diego CA, US
Andrew du Preez - San Diego CA, US
Louis Botha - San Diego CA, US
Johan (Hendrik) Conroy - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/00
G06F 13/36
G06F 15/76
H04M 3/00
H04W 4/00

US Classification:

710110, 710306, 710315, 712 37, 712 38, 455418, 455419, 455466

Abstract:

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

US Patent:

7716528, May 11, 2010

Filed:

Nov 30, 2004

Appl. No.:

11/000805

Inventors:

Frederic Hayem - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 11/00

US Classification:

714 30, 714 21, 714 35

Abstract:

Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

US Patent:

7984216, Jul 19, 2011

Filed:

Aug 18, 2009

Appl. No.:

12/543008

Inventors:

Frederic Hayem - San Diego CA, US
Andrew du Preez - San Diego CA, US
Louis Botha - San Diego CA, US
Johan (Hendrik) Conroy - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/00
G06F 1/04
G06F 1/12
G06F 5/06
H04M 11/00
H04M 1/00

US Classification:

710110, 713600, 455403, 4555521, 4555531

Abstract:

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

US Patent:

8005503, Aug 23, 2011

Filed:

Dec 11, 2003

Appl. No.:

10/733856

Inventors:

Frederic Hayem - San Diego CA, US
Leo Borromeo - San Diego CA, US
Michiel Lötter - San Diego CA, US

International Classification:

H04M 1/00

US Classification:

4555521, 455411, 4554351, 455436, 455500, 370241, 370331

Abstract:

A method for effecting timing synchronization within a multi-mode communication device is disclosed herein. The method includes configuring a host baseband processor of the multi-mode device to operate in accordance with a first wireless communications protocol of a first wireless communications system. A baseband co-processor of the device is also configured to operate in accordance with a second wireless communications protocol of a second wireless communications system. The method includes establishing, within the device, timing synchronization between the first and second communication systems on the basis of timing information transferred to the host baseband processor from the baseband co-processor.

US Patent:

8031757, Oct 4, 2011

Filed:

Jun 25, 2010

Appl. No.:

12/823308

Inventors:

Louis Jacobus Botha - San Diego CA, US
Frederic Christian Hayem - San Diego CA, US
Hendrik Johannes Conroy - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 3/36
H04L 12/66
G01S 31/02

US Classification:

375212, 375341, 370355

Abstract:

A method for operating a Radio Frequency (RF) receiver of a wireless terminal. During a first time interval, an RF front end is enabled and the RF receiver receives and processes an RF signal, e. g. , a Wideband Code Division Multiple Access (WCDMA) signal, to produce a baseband signal and to store samples of the baseband signal. During a second time interval that differs from the first time interval, the RF front end is disabled and the RF receiver processes the plurality of samples of the baseband signal of the first time interval to measure signal strengths of a plurality of pilot signals present in the baseband signal of the first time interval. Finally, during a third time interval that differs from the first time interval and the second time interval, the RF front end is enabled and the RF receiver receives and processes an RF signal of the third time interval to extract data there from. Memory is shared between the first, second, and third time intervals for different uses.

US Patent:

8161217, Apr 17, 2012

Filed:

Jul 19, 2011

Appl. No.:

13/186311

Inventors:

Frederic Hayem - San Diego CA, US
Andrew du Preez - San Diego CA, US
Louis Botha - San Diego CA, US
Johan (Hendrik) Conroy - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/00
G06F 13/36
G06F 15/76
H04M 3/00
H04M 1/00

US Classification:

710110, 710306, 710315, 712 37, 712 38, 455418, 455419, 4555521, 4555531

Abstract:

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

US Patent:

8423077, Apr 16, 2013

Filed:

Dec 11, 2003

Appl. No.:

10/733861

Inventors:

Frederic Hayem - San Diego CA, US
Leo Borromeo - San Diego CA, US
Michiel Lötter - San Diego CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04M 1/00

US Classification:

4555521, 455411, 4554351, 455436, 455500, 370241, 370331, 370503, 370350, 370304, 709102, 709248, 709202

Abstract:

A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.