Gary G Morrison

US Patent:

6418489, Jul 9, 2002

Filed:

Jan 18, 2000

Appl. No.:

09/488368

Inventors:

Kristen L. Mason - Austin TX
Gary R. Morrison - Austin TX
Jeffrey M. Polega - Austin TX
Donald L. Tietjen - Austin TX
Frank C. Galloway - Dripping Springs TX
Charles Edward Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX
Robert Bradford Cohen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1328

US Classification:

710 22, 710 54, 710266, 711100, 711105, 711169

Abstract:

Direct memory access controller (DMA) ( ) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) ( ). A master DMA engine (MDE) ( ) includes a top level state machine ( ) to coordinate a context save state machine ( ), a parse state machine ( ), and a running state machine ( ). An loop control descriptor (LCD) queue ( ) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

US Patent:

6421744, Jul 16, 2002

Filed:

Oct 25, 1999

Appl. No.:

09/426009

Inventors:

Gary R. Morrison - Austin TX
Kristen L. Mason - Austin TX
Frank C. Galloway - Dripping Springs TX
Charles E. Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX
Jeffrey M. Polega - Austin TX
Donald L. Tietjen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 928

US Classification:

710 22, 710 68, 710 23, 710 31, 710 33, 711148, 711162, 711202

Abstract:

Direct memory access controller (DMAC) ( ) adapted to directly execute C language style FOR tasks assigned by a processor ( ), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) ( ), each to perform an arithmetic or logical operation, and a FOR task controller ( ) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

US Patent:

6542940, Apr 1, 2003

Filed:

Jan 18, 2000

Appl. No.:

09/488367

Inventors:

Gary R. Morrison - Austin TX
Peter J. Myers - Austin TX
Charles Edward Nuckolls - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1328

US Classification:

710 22, 710 58, 713502, 714 47

Abstract:

Method for maintaining an execution interval for a task requestor to a DMA. A timer is provided with two counters, one ( ) to maintain the execution interval and the second ( ) to track the execution time of a task in the DMA. Each task has a predetermined execution time allowance. A task acknowledge (TACK) signal enables the tracking. A task request signal (TREQ) is generated during each execution interval until the execution time allowance is completed. The length of the second counter is less than the first counter. In one embodiment, if the first counter expires before the execution time allowance is completed, a task error signal (TERR) is illustrated.

US Patent:

6581086, Jun 17, 2003

Filed:

Jan 18, 2000

Appl. No.:

09/488366

Inventors:

Gary R. Morrison - Austin TX
Charles Edward Nuckolls - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 738

US Classification:

708523

Abstract:

A multiply and accumulate (MAC) unit ( ) having a multiplier ( ) and an adder ( ) for providing a calculated result of a MAC operation, an accumulator ( ) for storing the calculated result, and a scaler unit ( ) for selecting a subset of the calculated result stored in the accumulator. The scaler unit receives information defining the subset as a predetermined number of contiguous bits and defining the location of the bits with respect to a radix point. In response to a detected error in the selection of the subset, the scaler unit selects a second subset, where the second subset also has a predetermined number of contiguous bits having a different location with respect to the radix point:.

US Patent:

6675235, Jan 6, 2004

Filed:

Jan 18, 2000

Appl. No.:

09/488363

Inventors:

Frank C. Galloway - Dripping Springs TX
Kristen L. Mason - Austin TX
Gary R. Morrison - Austin TX
Charles Edward Nuckolls - Austin TX
Jennifer L. McKeown - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1314

US Classification:

710 29, 712209, 712210, 364200

Abstract:

An execution unit ( ) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function execution is pipelined through the execution unit, where an input unit ( ) stores information, while a function logic unit ( ) processes data and an output unit ( ) holds results to be output. The execution unit ( ) allows for data rate distortion, in applications such as data compression, where the amount of data received is different from the amount of data generated as output.

US Patent:

7213169, May 1, 2007

Filed:

Apr 3, 2003

Appl. No.:

10/406650

Inventors:

John Steven Dodson - Pflugerville TX, US
Michael Stephen Floyd - Austin TX, US
Jerry Don Lewis - Round Rock TX, US
Gary Alan Morrison - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 30

Abstract:

An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written. The time stamp trace record includes a count of the number of address transactions that were not converted to trace records.

US Patent:

7302616, Nov 27, 2007

Filed:

Apr 3, 2003

Appl. No.:

10/406649

Inventors:

John Steven Dodson - Pflugerville TX, US
Jerry Don Lewis - Round Rock TX, US
Gary Alan Morrison - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 45

Abstract:

An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

US Patent:

7373471, May 13, 2008

Filed:

Feb 9, 2005

Appl. No.:

11/054447

Inventors:

Mark Andrew Brittain - Pflugerville TX, US
Warren Edward Maule - Cedar Park TX, US
Gary Alan Morrison - Austin TX, US
Jeffrey Adam Stuecheli - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711167

Abstract:

Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.