Gary C Ward

US Patent:

60922028, Jul 18, 2000

Filed:

May 22, 1998

Appl. No.:

9/084078

Inventors:

Leonard Scott Veil - Campbell CA
Gary Paul Ward - Sunnyvale CA
Richard Alan Weiss - Los Altos Hills CA
Eric Alan Murray - Los Gatos CA

Assignee:

N*Able Technologies, Inc. - Cupertino CA

International Classification:

H04L 900
G06F 1100

US Classification:

713201

Abstract:

A method and system for secure transactions. The method and system comprise a security co-processor and an interface for interfacing the security co-processor to a host computer system. The method and system wherein secure transaction processing is performed locally in the security co-processor and non-secure transaction processing is performed in the host computer system. The method and system further include means for providing trusted input coupled to the security co-processor. In addition, the method and system include a second interface coupled to the security co-processor for receiving sensitive data from a smart card, and a trusted display coupled to the security co-processor for providing true transaction information. One advantage of the method and system in accordance with the present invention is that transactions are protected from unauthorized intrusion and, in addition, participation is proven so that transactions cannot be repudiated. Another advantage is that the method and system maintain compatibility with smart cards technology.

US Patent:

20180314431, Nov 1, 2018

Filed:

Apr 28, 2017

Appl. No.:

15/582459

Inventors:

- Santa Clara CA, US
Jonathon EVANS - Santa Clara CA, US
Gary Ward - Santa Clara CA, US
Philip Browning Johnson - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.

US Patent:

20170161099, Jun 8, 2017

Filed:

Dec 3, 2015

Appl. No.:

14/958714

Inventors:

- Santa Clara CA, US
Gary Ward - Santa Clara CA, US
Wei-Je Robert Huang - Fremont CA, US
Philip Browning Johnson - San Jose CA, US

International Classification:

G06F 9/48

Abstract:

A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.

US Patent:

20170161100, Jun 8, 2017

Filed:

Dec 3, 2015

Appl. No.:

14/958719

Inventors:

- Santa Clara CA, US
Gary Ward - Santa Clara CA, US
Wei-Je Robert Huang - Fremont CA, US
Philip Browning Johnson - San Jose CA, US

International Classification:

G06F 9/48
G06F 9/52

Abstract:

A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.

US Patent:

20140109102, Apr 17, 2014

Filed:

Oct 12, 2012

Appl. No.:

13/651131

Inventors:

- Santa Clara CA, US
Gary WARD - Santa Clara CA, US
M. Wasiur RASHID - San Jose CA, US
Lincoln G. GARLICK - Santa Clara CA, US
Wojciech Jan Truty - Redwood City CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 9/48

US Classification:

718103

Abstract:

A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.