George William Alexander

US Patent:

6516006, Feb 4, 2003

Filed:

Feb 16, 1999

Appl. No.:

09/250161

Inventors:

Robert M. Walker - Rougemont NC
Stephen M. Camacho - Durham NC
George W. Alexander - Durham NC

Assignee:

Mitsubishi Electric and Electronics U.S.A., Inc. - Cypress CA

International Classification:

H04J 306

US Classification:

370503, 370516, 370522, 375356, 375357, 375371

Abstract:

A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

US Patent:

6653875, Nov 25, 2003

Filed:

Mar 11, 2002

Appl. No.:

10/095318

Inventors:

Torsten Partsch - Chapel Hill NC
George W. Alexander - Durham NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03L 706

US Classification:

327158, 327149, 327161

Abstract:

A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a delayed clock signal. The forward delay circuit adjustably shifts in time the delayed clock signal relative to the reference clock signal. An inverter receives the delayed clock signal and issues an inverted delayed clock signal. A feedback delay circuit receives a selected one of the delayed and the inverted delayed clock signals, and issues a feedback clock signal that is shifted in time relative to the selected one of the delayed and the inverted delayed clock signals. The feedback clock signal is compared to the reference clock signal. The time shift of the delayed clock signal is adjusted to thereby time-align the reference clock signal and the feedback clock signal.

US Patent:

6693473, Feb 17, 2004

Filed:

Mar 19, 2002

Appl. No.:

10/100713

Inventors:

George W. Alexander - Durham NC
Jinhwan Lee - Raleigh NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03L 706

US Classification:

327158, 327149

Abstract:

A delay lock loop circuit includes a forward delay circuit having a plurality of delay elements. Each delay element has a delay time of one unit delay time. The forward delay circuit and each of the delay elements are powered by a supply voltage. The supply voltage is set to thereby set the duration of a unit delay time. Moreover, a feedback delay circuit is provided in order to cause a feedback delay time being substantially equal to a propagation delay of the IC. As the operating conditions of IC change, and the propagation delay thereof increases or decreases, the feedback delay time changes accordingly, and thus the delay caused by forward delay circuit tracks the change in the propagation delay of the IC.

US Patent:

6760261, Jul 6, 2004

Filed:

Sep 25, 2002

Appl. No.:

10/254305

Inventors:

Torsten Partsch - Chapel Hill NC
George William Alexander - Durham NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 700

US Classification:

36518905, 36523008, 365193

Abstract:

A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.

US Patent:

6765419, Jul 20, 2004

Filed:

Mar 11, 2002

Appl. No.:

10/094793

Inventors:

George W. Alexander - Durham NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03L 706

US Classification:

327158, 327149

Abstract:

A delay lock loop circuit for aligning in time a reference clock signal with an internal feedback clock signal includes a forward delay circuit that receives the reference clock signal. The forward delay circuit includes a forward delay line having a plurality of electrically interconnected delay blocks. Each of the delay blocks includes a predetermined number of electrically interconnected delay units. Disabling means deactivate the one or more delay blocks when the delay blocks are not needed in order to time align the reference clock signal and the internal feedback clock signal.

US Patent:

6777990, Aug 17, 2004

Filed:

Mar 19, 2002

Appl. No.:

10/100639

Inventors:

Torsten Partsch - Chapel Hill NC
George W. Alexander - Durham NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03L 706

US Classification:

327149, 327158

Abstract:

A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.

US Patent:

6809978, Oct 26, 2004

Filed:

May 13, 2002

Appl. No.:

10/144597

Inventors:

George William Alexander - Durham NC
Steven Michael Baker - Morrisville NC

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 704

US Classification:

365211, 365212, 365149, 36518907

Abstract:

A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a voltage of a network of the integrated circuit and regulating a voltage of an internal voltage generator of the integrated circuit based on the comparing.

US Patent:

6845048, Jan 18, 2005

Filed:

Sep 25, 2002

Appl. No.:

10/255767

Inventors:

George W. Alexander - Durham NC, US
Jennifer F. Huckaby - Raleigh NC, US
Steven M. Baker - Apex NC, US
David S. Ma - Cary NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 114074
G11C 114193
H03K 17693

US Classification:

36518902, 36518909, 365226, 327407, 327 99

Abstract:

A system and method for monitoring internal voltage sources in an integrated circuit, such as a DRAM integrated circuit, includes an internal analog multiplexing circuit, an internal analog-to-digital converter, and an interface circuit. Through the analog multiplexing circuit, the analog-to-digital converter sequentially connects to each voltage source and converts the measured voltage level of the source to a binary word. The interface circuit presents the binary word, e. g. , serially, to test equipment off the integrated circuit.

Address:

6855 166 Pl SE UNIT 6, Bellevue, WA 98006

VIN:

JS1GT77A372103077

Make:

ISUZU

Model:

OASIS 5DR S 7-PASSENGER

Year:

2007