George N Bajor

US Patent:

6365953, Apr 2, 2002

Filed:

Apr 1, 1999

Appl. No.:

09/283530

Inventors:

Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 2900

US Classification:

257513, 257506, 257510, 257520

Abstract:

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

US Patent:

6441447, Aug 27, 2002

Filed:

Aug 11, 1999

Appl. No.:

09/367325

Inventors:

Joseph A. Czagas - Palm Bay FL
George Bajor - Melbourne FL
Leonel Enriquez - Melbourne FL
Chris A. McCarty - Melbourne FL

Assignee:

Intersil Corporation - Palm Bay FL

International Classification:

H01L 2976

US Classification:

257379, 257536, 257537, 257766, 257904

Abstract:

A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

US Patent:

6551897, Apr 22, 2003

Filed:

Nov 16, 2001

Appl. No.:

09/993968

Inventors:

Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 21762

US Classification:

438404, 438406, 438437

Abstract:

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches. Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

US Patent:

6798024, Sep 28, 2004

Filed:

Jun 29, 2000

Appl. No.:

09/607080

Inventors:

Donald Hemmenway - Melbourne FL
Jose Delgado - Valkaria FL
John Butler - Palm Bay FL
Anthony Rivoli - Palm Bay FL
Michael D. Church - Sebastian FL
George V. Rouse - Indialantic FL
Lawrence G. Pearce - Palm Bay FL
George S. Bajor - Melbourne FL

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H01L 2976

US Classification:

257370

Abstract:

A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistors fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient.

US Patent:

6812108, Nov 2, 2004

Filed:

Mar 19, 2003

Appl. No.:

10/393181

Inventors:

Donald Hemmenway - Melbourne FL
Jose Delgado - Valkaria FL
John Butler - Palm Bay FL
Anthony Rivoli - Palm Bay FL
Michael D. Church - Sebastian FL
George V. Rouse - Indialantic FL
Lawrence G. Pearce - Palm Bay FL
George Bajor - Melbourne FL

Assignee:

Intersil Corporation - Palm Bay FL

International Classification:

H01L 2120

US Classification:

438385, 438330, 438382

Abstract:

A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistors fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient.

US Patent:

47710160, Sep 13, 1988

Filed:

Apr 24, 1987

Appl. No.:

7/042135

Inventors:

George Bajor - Melbourne FL
Joseph S. Raby - Melbourne FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 2120
H01L 2176

US Classification:

437180

Abstract:

A method of forming a high quality silicon on insulator semiconductor device using wafer bonding. The annealing time for the wafer bonding process is substantially reduced through the use of a rapid thermal annealer, thereby resulting in minimizing the redistribution of the doping concentration resulting from the annealing process.

US Patent:

57448523, Apr 28, 1998

Filed:

Sep 19, 1996

Appl. No.:

8/710694

Inventors:

Jack H. Linn - Melbourne FL
George Bajor - Melbourne FL
George V. Rouse - Indialantic FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 2906

US Classification:

257506

Abstract:

A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.

US Patent:

50289730, Jul 2, 1991

Filed:

Jun 19, 1989

Appl. No.:

7/367788

Inventors:

George S. Bajor - Melbourne FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 2972
H01L 2348
H01L 2940

US Classification:

357 34

Abstract:

A bipolar transistor structure having single crystal emitter, base and collector regions a first emitter contact layer of a higher bandgap than the single crystal and polycrystalline forms of the semiconductor material which forms the emitter and of the same conductivity type as the emitter, and a second emitter contact layer of a substantially polycrystalline form of the semiconductor material and of the same conductivity type as the emitter, on the first emitter contact layer. The higher bandgap first emitter contact layer serves as a barrier for the minority carriers, thus enhancing the emitter efficiency.