George T Conner

US Patent:

6486693, Nov 26, 2002

Filed:

May 19, 2000

Appl. No.:

09/577255

Inventors:

George Conner - Los Gatos CA
Peter Reichert - Thousand Oaks CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3126

US Classification:

324765, 3241581, 714700

Abstract:

An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.

US Patent:

6879175, Apr 12, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/404900

Inventors:

George W. Conner - Los Gatos CA, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R031/26

US Classification:

324765, 324713

Abstract:

A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

US Patent:

7208937, Apr 24, 2007

Filed:

Feb 17, 2005

Appl. No.:

11/060239

Inventors:

George W. Conner - Los Gatos CA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 31/28

US Classification:

3241581

Abstract:

A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

US Patent:

49337360, Jun 12, 1990

Filed:

Mar 10, 1989

Appl. No.:

7/323068

Inventors:

George W. Conner - Ben Lomond CA
Raymond G. Donald - San Jose CA
Ronald L. Cline - Los Gatos CA

Assignee:

North American Philips Corporation, Signetics Division - Sunnyvale CA

International Classification:

H01L 2704
G11C 1140

US Classification:

357 50

Abstract:

A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16). A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and an opposite-conductivity buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency. Connective regions (46) extend from the buried web to the upper semiconductor surface to contact electrical leads (54) typically arranged in a parallel pattern. The maximum dopant concentration in the intermediate cell regions occurs vertically within 20% of their mid-points.

US Patent:

47274093, Feb 23, 1988

Filed:

Aug 5, 1985

Appl. No.:

6/763063

Inventors:

George W. Conner - Ben Lomond CA
Ronald L. Cline - Los Gatos CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H01L 2904

US Classification:

357 59

Abstract:

A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

US Patent:

52683141, Dec 7, 1993

Filed:

Feb 3, 1992

Appl. No.:

7/830783

Inventors:

George W. Conner - Ben Lomond CA

Assignee:

Philips Electronics North America Corp. - New York NY

International Classification:

H01L 21331

US Classification:

437 31

Abstract:

A bipolar transistor device having reduced collector-base capacitance and advantageous extrinsic base resistance properties is fabricated by a self-aligned process. Successively formed first and second self-aligned masking spacers are utilized to define the collector-base junction area and to permit the conductivity of base link and base contact portions of the extrinsic base to be independently established.

US Patent:

46945660, Sep 22, 1987

Filed:

Jul 19, 1985

Appl. No.:

6/757185

Inventors:

George W. Conner - Ben Lomond CA
Raymond G. Donald - San Jose CA
Ronald L. Cline - Los Gatos CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H01L 21265
H01L 2972
H01L 21225

US Classification:

437 48

Abstract:

A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.

US Patent:

57941750, Aug 11, 1998

Filed:

Sep 9, 1997

Appl. No.:

8/926117

Inventors:

George W. Conner - Los Gatos CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 1100

US Classification:

702119

Abstract:

Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.