George W Conner

US Patent:

6469493, Oct 22, 2002

Filed:

Aug 1, 1995

Appl. No.:

08/510079

Inventors:

George W. Conner - Thousand Oaks CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 1512

US Classification:

3241581, 324765, 324763

Abstract:

Automatic test equipment implemented with low cost CMOS components. Despite the use of CMOS circuitry, which generally has poor timing accuracy, the disclosed test equipment achieves good timing accuracy through the use of several techniques. A delay locked loop is used to compensate for timing variations caused by process variation and slowly varying changes in operating temperature. A frequency dependent heating element is used to avoid temperature induced changes in propagation delays caused by rapid variations in the heat generated by the CMOS circuitry when the operating frequency changes. The design also reduces the number of circuit elements in the critical timing paths which process signals which vary with programmed frequency. To achieve this goal, a continuously running, fixed frequency reference clock is delayed by a fractional amount of one clock period. A counter, also clocked at the reference clock frequency, counts full clock periods.

US Patent:

6486693, Nov 26, 2002

Filed:

May 19, 2000

Appl. No.:

09/577255

Inventors:

George Conner - Los Gatos CA
Peter Reichert - Thousand Oaks CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3126

US Classification:

324765, 3241581, 714700

Abstract:

An automatic test system useful for testing source synchronous devices at high speed. The data outputs of the device under test are routed to channel circuitry within the test system through coaxial cables. The test system includes a buffer amplifier on a device interface board to fan out the DATA CLOCK generated by the device under test to that channel circuitry. The interconnection between the buffer amplifier and the channel circuitry is provided through a coax with low dielectric constant, to compensate for the delay introduced by the buffer amplifier.

US Patent:

6879175, Apr 12, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/404900

Inventors:

George W. Conner - Los Gatos CA, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R031/26

US Classification:

324765, 324713

Abstract:

A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

US Patent:

7046027, May 16, 2006

Filed:

Oct 15, 2004

Appl. No.:

10/966480

Inventors:

George W. Conner - Camarillo CA, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 31/28
G01R 31/26

US Classification:

324765, 3241581, 324 731

Abstract:

A signal interface to connect a semiconductor tester to a device under test. The Interface includes a generic component and customized component. The generic component includes multiple copies of electronic elements that can be connected in signal paths between the tester and the device under test. The customized component is constructed for a specific device under test and provides connections between generic contact points on the generic component and test points on the device under test. In addition, the customized component has conductive members that can be used to interconnect the electronic elements on the generic component. The connections configure the electronic elements into signal conditioning circuitry, thereby providing signal paths through the interface that are compatible with the I/O characteristics of specific test points on a device under test. The generic and the customized components may be fabricated on semiconductor wafers.

US Patent:

7174279, Feb 6, 2007

Filed:

Mar 31, 2004

Appl. No.:

10/813712

Inventors:

George W. Conner - Camarillo CA, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 15/00

US Classification:

702189, 324527

Abstract:

A test system with easy to fabricate hardware to make measurements on differential signals. The two legs of a differential signal are applied to a comparator. A variable bias is introduced into the comparison operation. By taking multiple measurements with different bias levels, the level of the differential signal may be determined. The time of measurements relative to the start of the signal can be varied to allow plots of the signal to be made. Variability of the signal caused by noise can be measured by collecting sets of data points with the same bias level at the same relative time. Circuitry for introducing bias into the comparison is disclosed that allows measurements to be made with a pre-packaged, commercially available high speed comparator.

US Patent:

7208937, Apr 24, 2007

Filed:

Feb 17, 2005

Appl. No.:

11/060239

Inventors:

George W. Conner - Los Gatos CA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 31/28

US Classification:

3241581

Abstract:

A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

US Patent:

7523007, Apr 21, 2009

Filed:

Jun 29, 2007

Appl. No.:

11/771389

Inventors:

Li Huang - Westlake Village CA, US
George W. Conner - Camarillo CA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 35/00

US Classification:

702 89

Abstract:

A calibration device is provided for use with automatic test equipment (ATE). The calibration device includes circuitry having a fanout circuit. The compare-side fanout circuit has an input connected to a first channel of the ATE and outputs connected to N (N>1) channels of the ATE, where the N channels do not include the first channel. The ATE propagates an edge on the first channel, and the fanout circuit transmits the edge to the N channels. Optionally, a calibration device for use with automatic test equipment includes a drive-side circuit. The drive-side circuit includes circuitry having multiple inputs connected to N (N>1) channels of the ATE and an output connected to a second channel of the ATE that is not one of the N channels. The ATE propagates an edge on each of the N-channels and the circuitry propagates each edge to the second channel of the ATE.

US Patent:

7593497, Sep 22, 2009

Filed:

Oct 31, 2005

Appl. No.:

11/263397

Inventors:

George W. Conner - Camarillo CA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

H04L 7/04

US Classification:

375362

Abstract:

A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.