George Skidmore

US Patent:

6762116, Jul 13, 2004

Filed:

Jun 12, 2002

Appl. No.:

10/167939

Inventors:

George D. Skidmore - Richardson TX

Assignee:

Zyvex Corporation - Richardson TX

International Classification:

H01L 2144

US Classification:

438598, 438 50, 438 51, 438 52, 438 53, 438689, 438690, 257414, 257415, 257416, 257417, 257254

Abstract:

A system and method is described for fabricating microcomponents onto pre-existing integrated electronics. One embodiment of the present invention provides additional process steps after completion of all electronics fabrication that may etch trough the oxide of any passivation layer that may be there to the single crystal silicon (SCS) of a silicon on insulator (SOI) integrated circuit. Once at the SCS level of the existing wafer, any number of microcomponents, such as connectors, receptacles, handles, tethers, and the like may preferably be fabricated onto the chip using relatively low temperature and inexpensive processing; thus, preferably preserving the integrity of the preexisting electronics.

US Patent:

6879016, Apr 12, 2005

Filed:

Oct 7, 2002

Appl. No.:

10/266726

Inventors:

George D. Skidmore - Plano TX, US
Aaron Geisberger - Plano TX, US
Matthew D. Ellis - Allen TX, US

Assignee:

Zyvex Corporation - Richardson TX

International Classification:

H01L029/00
H01L029/06

US Classification:

257499, 257622, 257623

Abstract:

A system and method is disclosed that strengthens the structural integrity of trench-fill electrical isolation techniques. One embodiment provides for etching a series of interlocking geometric trenches into a device layer and filling the trenches with a non-conductive dielectric material. The dielectric material establishes electrical isolation while the interlocking geometric trenches strengthen the structural integrity of the separation by providing at least one surface on the interlocking separation that experiences a compression force for each direction that the electrically isolated MEMS component is moved.

US Patent:

6923669, Aug 2, 2005

Filed:

Feb 13, 2004

Appl. No.:

10/778460

Inventors:

Kenneth Tsui - Richardson TX, US
Aaron Geisberger - Dallas TX, US
George Skidmore - Richardson TX, US

Assignee:

Zyvex Corporation - Richardson TX

International Classification:

H01R013/627

US Classification:

439353

Abstract:

A MEMS microconnector including a compliant handle and a deflectable connection member. The compliant handle is configured to frictionally engage a manipulation probe. The deflectable connection member includes a first end coupled to the handle and a second end configured to deflect and thereby engage a receptacle in response to disengagement of the manipulation probe from the handle.

US Patent:

7224035, May 29, 2007

Filed:

Oct 7, 2002

Appl. No.:

10/266724

Inventors:

George D. Skidmore - Plano TX, US
Gregory A. Magel - Dallas TX, US
Charles G. Roberts - McKinney TX, US

Assignee:

Zyvex Corporation - Richardson TX

International Classification:

H01L 27/12

US Classification:

257414, 257E21545, 438 48

Abstract:

Fabricating electrical isolation properties into a MEMS device is described. One embodiment comprises a main substrate layer of a high-resistivity semiconductor material, such as high-resistivity silicon. The high-resistivity substrate is then controllably doped to provide a region of high-conductivity in the main substrate. Electrical isolation is achieved in such an embodiment by patterning the high-conductivity region either by masking the main substrate during the doping or etching through the doped, high-conductivity region in order to form regions of high conductivity. Effective isolation results from confinement of electrical currents to the lowest-resistance path. An alternative embodiment employs the fabrication of pn junctions and the use of reverse biasing to enhance the electrical isolation. A further embodiment comprises a main substrate layer of low-resistivity semiconductor material with a layer of insulator deposited thereon. High-conductivity or low-resistivity material is then grown on top of the insulator to create electrically isolated conductors.

US Patent:

7227140, Jun 5, 2007

Filed:

Sep 23, 2004

Appl. No.:

10/948385

Inventors:

George Skidmore - Richardson TX, US
Matthew D. Ellis - Allen TX, US
Aaron Geisberger - Dallas TX, US
Kenneth Bray - Garland TX, US
Kimberly Tuck - Dallas TX, US
Robert Folaron - Plano TX, US

Assignee:

Zyvex Instruments, LLC - Richardson TX

International Classification:

G21G 5/00

US Classification:

250307, 25049221, 2504923, 25044211, 702 84, 438 17

Abstract:

A method including, in one embodiment, severing a sample at least partially from a substrate by cutting the substrate with a focused ion beam (FIB), capturing the substrate sample by activating a grasping element, and separating the captured sample from the substrate. The captured sample may be separated from the substrate and transported to an electron microscope for examination.

US Patent:

7326293, Feb 5, 2008

Filed:

Mar 25, 2005

Appl. No.:

11/089814

Inventors:

John N. Randall - Richardson TX, US
Jingping Peng - Plano TX, US
George D. Skidmore - Richardson TX, US
Christof Baur - Dallas TX, US
Robert J. Folaron - Plano TX, US

Assignee:

Zyvex Labs, LLC - Richardson TX

International Classification:

C30B 19/08

US Classification:

117 55, 117 54, 117 86, 117 94, 117 95

Abstract:

A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.

US Patent:

7622717, Nov 24, 2009

Filed:

Dec 3, 2007

Appl. No.:

11/949367

Inventors:

George D. Skidmore - Richardson TX, US
Christopher G. Howard - Dallas TX, US

Assignee:

DRS Sensors & Targeting Systems, Inc. - Dallas TX

International Classification:

H01L 31/00

US Classification:

2503381

Abstract:

A pixel structure for use in an infrared imager is provided. The pixel structure includes a substrate and a bolometer. The bolometer includes a transducer that has a spaced apart relationship with respect to the substrate and has an electrical resistance that varies in response to changes in the temperature of the transducer. The bolometer also includes an absorber that has a spaced apart relationship with respect to the transducer and has a thermal connection to the transducer permitting radiation absorbed by the absorber to heat the transducer. The absorber has a top side defining a recess or channel in the absorber. The recess or channel is adapted to effect the propagation path of a portion of radiation received by the absorber such that the radiation portion is absorbed by the absorber rather than exiting the absorber. The recess or channel also decreases the thermal mass of the bolometer.

US Patent:

7799132, Sep 21, 2010

Filed:

Dec 13, 2007

Appl. No.:

11/955845

Inventors:

John N. Randall - Richardson TX, US
Jingping Peng - Plano TX, US
George D. Skidmore - Richardson TX, US
Christof Baur - Dallas TX, US
Richard E. Stallcup - Little Elm TX, US
Robert J. Folaron - Plano TX, US

Assignee:

Zyvex Labs, LLC - Richardson TX

International Classification:

C30B 25/04

US Classification:

117 84, 117 89, 117 94, 117104, 117105

Abstract:

A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.