Gerald Paul Martinez

US Patent:

60641088, May 16, 2000

Filed:

Sep 2, 1997

Appl. No.:

8/922983

Inventors:

Gerald M. Martinez - Long Beach CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

H01L 2941

US Classification:

257532

Abstract:

An integrated, interdigitated capacitor incorporates all layers of an I. C. fabrication process into its design to produce a multi-layer high-capacitance device. For example, a "two-metal, two-poly" CMOS fabrication process is used to produce a capacitor having five interdigitated conductive plates, which when interconnected produce a total capacitance at least twice as great as a conventional two-plate capacitor of the same area, while requiring no additional I. C. processing steps. The invention's conductive plates and interconnections are arranged so that interconnection traces stay within strict design limits intended to insure reliable connections, while keeping the area required for the interconnections small.