Gerald D Schmidt

US Patent:

20220404995, Dec 22, 2022

Filed:

Jul 27, 2022

Appl. No.:

17/874544

Inventors:

- Singapore, SG
Gerald Schmidt - San Jose CA, US
Tsahi Daniel - Palo Alto CA, US
Saurabh Shrivastava - Saratoga CA, US

International Classification:

G06F 3/06
G11C 15/04
H03K 19/17728
H04L 45/745

Abstract:

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

US Patent:

20210329104, Oct 21, 2021

Filed:

May 26, 2021

Appl. No.:

17/330782

Inventors:

- Singapore, SG
Tsahi Daniel - Palo Alto CA, US
Gerald Schmidt - San Jose CA, US

International Classification:

H04L 29/06
H04L 12/935

Abstract:

Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

US Patent:

20210058087, Feb 25, 2021

Filed:

Oct 14, 2020

Appl. No.:

17/070771

Inventors:

- Singapore, SG
Gerald Schmidt - San Jose CA, US
Srinath Atluri - Fremont CA, US
Weinan Ma - San Jose CA, US
Shrikant Sundaram Lnu - San Jose CA, US

International Classification:

H03K 21/02
H04L 12/863
H04L 12/861

Abstract:

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

US Patent:

20210034269, Feb 4, 2021

Filed:

Aug 18, 2020

Appl. No.:

16/996749

Inventors:

- Singapore, SG
Gerald Schmidt - San Jose CA, US
Tsahi Daniel - Palo Alto CA, US
Saurabh Shrivastava - Saratoga CA, US

International Classification:

G06F 3/06
G11C 15/04
H03K 19/17728
H04L 12/741

Abstract:

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

US Patent:

20200374240, Nov 26, 2020

Filed:

Aug 13, 2020

Appl. No.:

16/992978

Inventors:

- Singapore, SG
Sachin Ramesh Gandhi - San Jose CA, US
Tsahi Daniel - Palo Alto CA, US
Gerald Schmidt - San Jose CA, US
Albert Fishman - Sunnyvale CA, US
Martin Leslie White - Sunnyvale CA, US
Zubin Shah - Santa Clara CA, US

International Classification:

H04L 12/933
G06F 3/06
H04L 12/715
H04L 12/741
H04L 29/06
H04L 29/08
H04L 12/935
G06F 16/00
G06F 40/205

Abstract:

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

US Patent:

20200351206, Nov 5, 2020

Filed:

May 15, 2020

Appl. No.:

16/875776

Inventors:

- Grand Cayman, KY
Gerald Schmidt - San Jose CA, US
Tsahi Daniel - Palo Alto CA, US
Saurabh Shrivastava - Saratoga CA, US

International Classification:

H04L 12/813
H04L 12/26
H04L 12/14

Abstract:

Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.

US Patent:

20200336423, Oct 22, 2020

Filed:

Jul 7, 2020

Appl. No.:

16/922895

Inventors:

- Grand Cayman, KY
Gerald Schmidt - San Jose CA, US
Tsahi Daniel - Palo Alto CA, US
Harish Krishnamoorthy - San Jose CA, US

International Classification:

H04L 12/741
G06F 16/00
G06F 16/22
G06F 16/9535
H04L 12/701

Abstract:

Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.

US Patent:

20180323789, Nov 8, 2018

Filed:

Jun 27, 2018

Appl. No.:

16/019780

Inventors:

- San Jose CA, US
Gerald Schmidt - San Jose CA, US
Srinath Atluri - Fremont CA, US
Weinan Ma - San Jose CA, US
Shrikant Sundaram Lnu - San Jose CA, US

International Classification:

H03K 21/02
H04L 12/861

Abstract:

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.