Glen A Gomes from 241 Vista Cove Cir, Sacramento, CA 95835, age 62, Phone: (916)9240285

Us Patents

Apparatus And Method For Successively Generating An Event To Establish A Total Delay Time That Is Greater Than Can Be Expressed By Specified Data Bits In An Event Memory
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US Patent:

6668331, Dec 23, 2003
Filed:

Mar 24, 2000
Appl. No.:

09/535031
Inventors:

Glen A. Gomes - Santa Clara CA
Anthony Le - Santa Clara CA
James Alan Turnquist - Santa Clara CA
Shigeru Sugamori - Santa Clara CA
Assignee:

Advantest Corp. - Tokyo
International Classification:

G06F 104
US Classification:

713401, 713400, 713500, 713502, 714715
Abstract:

An apparatus and method in an event based test system for testing an electronics device under test (DUT). The apparatus includes an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and an additional delay time inserted in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The additional delay time is inserted by replicating the timing data and the event type data of the event immediately prior to the specified event.

Event Pipeline And Summing Method And Apparatus For Event Based Test System
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US Patent:

7010452, Mar 7, 2006
Filed:

Jul 12, 2003
Appl. No.:

10/618387
Inventors:

Glen Gomes - Santa Clara CA, US
Anthony Le - Santa Clara CA, US
Assignee:

Advantest Corp. - Tokyo
International Classification:

G06F 11/00
US Classification:

702117, 702118, 702124, 714724
Abstract:

An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.

Event Processing Apparatus And Method For High Speed Event Based Test System
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US Patent:

7171602, Jan 30, 2007
Filed:

Dec 13, 2002
Appl. No.:

10/318959
Inventors:

Glen Gomes - Santa Clara CA, US
Anthony Le - Santa Clara CA, US
Assignee:

Advantest Corp. - Tokyo
International Classification:

G01R 31/28
G06F 11/00
US Classification:

714744, 714742, 714738
Abstract:

An apparatus and method for computing event timing for high speed event based test system. The event processing apparatus includes an event memory for storing event data of each event where the event data includes timing data for each event which is formed with an integer multiple of a clock period and a fraction of the clock period, an event summing logic for accumulating the timing data and producing the accumulated timing data in a parallel form, and an event generator for generating events specified by the event data based on the accumulated timing data received in the parallel form from the event summing logic. The events in the event data are specified as groups of events where each group of event is configured by one base event and at least one companion event.

Providing Precise Timing Control Between Multiple Standardized Test Instrumentation Chassis
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US Patent:

7366939, Apr 29, 2008
Filed:

Aug 3, 2005
Appl. No.:

11/196873
Inventors:

Anthony Le - Santa Clara CA, US
Glen Gomes - Santa Clara CA, US
Assignee:

Advantest Corporation - Ora-Gun
International Classification:

G06F 1/12
US Classification:

713400, 713503
Abstract:

Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Circuit Card Synchronization Within A Standardized Test Instrumentation Chassis
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US Patent:

7437588, Oct 14, 2008
Filed:

Aug 3, 2005
Appl. No.:

11/196996
Inventors:

Anthony Le - Santa Clara CA, US
Glen Gomes - Santa Clara CA, US
Assignee:

Advantest Corporation - Tokyo
International Classification:

G06F 1/12
US Classification:

713400
Abstract:

Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Providing Precise Timing Control Within A Standardized Test Instrumentation Chassis
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US Patent:

7437589, Oct 14, 2008
Filed:

Aug 3, 2005
Appl. No.:

11/197022
Inventors:

Anthony Le - Santa Clara CA, US
Glen Gomes - Santa Clara CA, US
Assignee:

Advantest Corporation - Tokyo
International Classification:

G06F 1/12
US Classification:

713400
Abstract:

Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Scaling Logic For Event Based Test System
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US Patent:

6557133, Apr 29, 2003
Filed:

Apr 5, 1999
Appl. No.:

09/286226
Inventors:

Glen A. Gomes - Santa Clara CA
Assignee:

Advantest Corp. - Tokyo
International Classification:

G01R 3128
US Classification:

714738
Abstract:

An event based test system having a scaling function for freely changing the timings of events for generating test signals for testing an electronics device under test (DUT) in proportion to a scale factor. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory, a summing and scaling logic for summing the timing data and modifying the timing data based on the scale factor to produce an overall time of each event relative to a predetermined reference point, and an event generator for generating each event based on the overall time.

Interferometry System And Methods For Substrate Processing
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US Patent:

20200011652, Jan 9, 2020
Filed:

Jul 3, 2018
Appl. No.:

16/026982
Inventors:

- Santa Clara CA, US
Cheuk Ming LEE - Castro Valley CA, US
Jae Myung YOO - San Jose CA, US
Glen Alan GOMES - San Jose CA, US
David Michael CORRIVEAU - Sacramento CA, US
Thang Duc NGUYEN - Milpitas CA, US
International Classification:

G01B 9/02
G03F 7/20
Abstract:

Processing systems and methods used in the manufacturing of flat panel displays (FPDs) are provided herein. In one embodiment, a processing system features a motion stage movably disposed on a base surface, one or more X-position interferometers, and a plurality of Y-position interferometers. The X-position interferometers include an X-position mirror fixedly coupled to the motion stage and an X-axis stationary module fixedly coupled a non-moving surface of processing system. Each of the plurality of Y-position interferometers include one of a first or second Y-position mirror fixedly coupled to the motion stage in orthogonal relationship to the one or more X-position mirrors and one of a first or a second Y-axis stationary module fixedly coupled to a non-moving surface of the processing system. Here, each of the Y-axis stationary modules is positioned to direct coherent radiation towards a respective Y-position mirror when the Y-position interferometer thereof is in an active arrangement.