Glen H Handlogten

US Patent:

6684232, Jan 27, 2004

Filed:

Oct 26, 2000

Appl. No.:

09/696911

Inventors:

Glen Howard Handlogten - Rochester MN
James Edward Phillips - Round Rock TX
Lawrence Joseph Powell - Round Rock TX
Martin Stanley Schmookler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 500

US Classification:

708204, 708497

Abstract:

During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

US Patent:

6973036, Dec 6, 2005

Filed:

Nov 1, 2001

Appl. No.:

10/004373

Inventors:

William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B017/00

US Classification:

370235, 3703954, 370462, 709234

Abstract:

A scheduler and scheduling method implement peak service distance using a next peak service time violated (NPTV) indication. A flow scheduled on a best effort or weighted fair queue (WFQ) is identified for servicing and a frame is dispatching from the identified flow. A next PSD time (NPT) being violated is checked for the flow. Responsive to identifying the next PSD time (NPT) being violated for the identified flow, a NPTV indicator is set. Alternatively, responsive to identifying the next PSD time (NPT) not being violated for the identified flow, the NPTV indicator is reset. A next PSD time (NPT) value is calculated for the flow. Checking for more frames to be dispatched from the flow is performed. Responsive to identifying no more frames to be dispatched from the flow, the NPTV indicator is utilized to identify a calendar for attaching the flow upon a new frame arrival for the flow. If the NPTV indicator is not set when the flow goes empty, upon a new frame arrival for the flow, the flow is attached to a weighted fair queue (WFQ) ring using a queue distance calculation.

US Patent:

6982986, Jan 3, 2006

Filed:

Nov 1, 2001

Appl. No.:

10/004217

Inventors:

William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

370412, 370468, 3703954

Abstract:

A QoS scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling with detecting and anticipating the end of a chain of flows. A first indicator is provided for indicating a number of flows being chained to a physical entry. A second indicator is provided for indicating when the first indicator has saturated. The second indicator is set active for a flow whose chaining causes the first indicator to saturate. During de-chaining of the flows from the physical entry, the second indicator is used to determine when the first indicator becomes accurate to begin decrementing the first indicator. The first indicator is decremented for detecting the end of the chain of flows. Responsive to the first indicator being not saturated, the first indicator is used for anticipating the end of a chain of flows. The first indicator and the second indicator include a predefined number of bits or n-bits.

US Patent:

6987760, Jan 17, 2006

Filed:

Apr 19, 2001

Appl. No.:

09/838395

Inventors:

Jean Louis Calvignac - Cary NC, US
William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
Marco C. Heddes - Cary NC, US
Joseph Franklin Logan - Raleigh NC, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US
Fabrice Jean Verplanken - La Gaude, FR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

370369, 370469, 370392, 709238

Abstract:

A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

US Patent:

7046676, May 16, 2006

Filed:

Nov 1, 2001

Appl. No.:

10/004440

Inventors:

William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

3703954, 370462, 709225, 709234

Abstract:

A QoS scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling with a cached status array. A plurality of calendars are provided for scheduling the flows. An active flow indicator is stored for each calendar entry in a calendar status array (CSA). A cache copy subset of the active flow indicators from the calendar status array (CSA) is stored in a cache. The calendar status array (CSA) is updated based upon a predefined calendar range and resolution. The cache copy subset of the active flow indicators from the calendar status array (CSA) is used to determine a given calendar for servicing. The subset of the active flow indicators from the calendar status array (CSA) is used to increment a current pointer (CP) by an identified number of positions up to a current time (CT) value, where the identified number of positions is equal to a variable number of inactive flow indicators up to the current time (CT) value and the identified number of positions has a maximum value equal to a number of entries in the cache.

US Patent:

7103051, Sep 5, 2006

Filed:

Nov 1, 2001

Appl. No.:

10/002416

Inventors:

William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

3703954, 37039541, 37039542, 37039543, 370412

Abstract:

A scheduler, scheduling method, and computer program product are provided for implementing Quality-of-Service (QoS) scheduling of a plurality of flows with aging time stamps. Subsets of time stamp data stored in a time stamp aging memory array are sequentially accessed. Each time stamp data subset contains time stamp data for a subplurality of flows. Guaranteed aging processing steps are performed for each flow utilizing the time stamp data subsets to identify and mark invalid calendar next time values. When a new frame arrival for an empty flow is identified, flow queue control block (FQCB) time stamp data and the flow time stamp data in the time stamp aging memory array are accessed. Based on the calendar to which the new frame is directed or the target calendar for the new frame, the target calendar next time valid bit of the time stamp aging memory array data is checked. When the target calendar next time valid bit is on, a target calendar next time value from the flow queue control block (FQCB) time stamp data is compared with a current time. When the target calendar next time is less than the current time, the target calendar next time valid bit is turned off to mark the target calendar next time as invalid.

US Patent:

7130270, Oct 31, 2006

Filed:

Jul 26, 2002

Appl. No.:

10/206170

Inventors:

Merwin Herscher Alferness - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 1/16

US Classification:

370235, 370399

Abstract:

In a scheduler circuit for a network processor, bandwidth assigned to a virtual path is allocated among virtual channels associated with the virtual path. The allocation of bandwidth among the virtual channels is varied dynamically as virtual channels become active or inactive.

US Patent:

7187684, Mar 6, 2007

Filed:

Nov 1, 2001

Appl. No.:

10/016518

Inventors:

William John Goetzinger - Rochester MN, US
Glen Howard Handlogten - Rochester MN, US
James Francis Mikos - Rochester MN, US
David Alan Norgaard - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

370412, 370468, 3703954

Abstract:

A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied to define a sequence in which flows are to be serviced. The scheduling queue includes at least a first subqueue and a second subqueue. The first subqueue has a first range and a first resolution, and the second subqueue has an extended range that is greater than the first range and a lower resolution that is less than the first resolution. Flows that are to be enqueued within the range of highest precision to the current pointer of the scheduling queue are attached to the first subqueue. Flows that are to be enqueued outside the range of highest precision from the current pointer of the scheduling queue are attached to the second subqueue. Numerous other aspects are provided.