Glenn C Abeln

US Patent:

7440313, Oct 21, 2008

Filed:

Nov 17, 2006

Appl. No.:

11/561206

Inventors:

Glenn C. Abeln - Austin TX, US
James D. Burnett - Meylan, FR
Lawrence N. Herr - Coupland TX, US
Jack M. Higman - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/00

US Classification:

365154, 365226, 365156

Abstract:

A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

US Patent:

7609541, Oct 27, 2009

Filed:

Dec 27, 2006

Appl. No.:

11/616635

Inventors:

James David Burnett - Austin TX, US
Glenn C. Abeln - Austin TX, US
Jack M. Higman - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/00

US Classification:

365154, 365226, 36518904

Abstract:

A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.

US Patent:

7879663, Feb 1, 2011

Filed:

Mar 8, 2007

Appl. No.:

11/683846

Inventors:

Mark D. Hall - Austin TX, US
Glenn C. Abeln - Austin TX, US
John M. Grant - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00
H01L 21/84

US Classification:

438164, 257E21564

Abstract:

A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

US Patent:

8062953, Nov 22, 2011

Filed:

Jul 30, 2008

Appl. No.:

12/182421

Inventors:

Mark D. Hall - Austin TX, US
Glenn C. Abeln - Buda TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/76

US Classification:

438429, 257E2156, 438296, 438430

Abstract:

A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

US Patent:

20060234467, Oct 19, 2006

Filed:

Apr 15, 2005

Appl. No.:

11/106822

Inventors:

Toni Van Gompel - Austin TX, US
Glenn Abeln - Austin TX, US
Peter Beckage - Austin TX, US
Kyle Gilliland - Pflugerville TX, US
Mohamad Jahanbani - Austin TX, US
James Burnett - Austin TX, US

International Classification:

H01L 21/76

US Classification:

438424000, 438425000

Abstract:

Divots () may particularly be a problem for isolation trenches () that are shallow. These divots () may have a negative impact on the performance of the integrated circuit (). Densification heating may be used to reduce the size and/or depth of these divots () during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches () with dielectric material (). This densification heating may improve the variation in threshold voltages of transistors (e.g. ) on an integrated circuit (), particularly SOI (silicon on insulator) devices. SRAM cells () in particular may benefit from this densification heating.

US Patent:

20120007155, Jan 12, 2012

Filed:

Sep 19, 2011

Appl. No.:

13/235580

Inventors:

MARK D. HALL - Austin TX, US
Glenn C. Abeln - Buda TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC - Austin TX

International Classification:

H01L 29/772

US Classification:

257288, 257E29242

Abstract:

A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

US Patent:

62075101, Mar 27, 2001

Filed:

Jul 29, 1999

Appl. No.:

9/363769

Inventors:

Glenn C. Abeln - Orlando FL
Robert Alan Ashton - Orlando FL
Samir Chaudhry - Orlando FL
Alan R. Massengale - Orlando FL
Jinghui Ning - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L21/8236

US Classification:

438276

Abstract:

A method for making an integrated circuit includes the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor. All of the implants needed to define the high voltage transistors are first performed throughout the active regions using the first mask. A separate single implant is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region. A gate dielectric layer is formed on the high and low voltage active regions for corresponding high and low voltage transistors, and gates are formed on the gate dielectric layers.

US Patent:

20230015944, Jan 19, 2023

Filed:

Jul 19, 2021

Appl. No.:

17/379213

Inventors:

- AUSTIN TX, US
Glenn Charles Abeln - Buda TX, US
Jorge Arturo Corso Samiento - Austin TX, US

International Classification:

G11C 29/42
G11C 29/18
G11C 7/10
H03K 19/017

Abstract:

A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request. The concept can also be used with parity bits on columns of the memory cells and a column decoder that selects bit lines associated with column address lines.