Glenn W Chapman

US Patent:

48106631, Mar 7, 1989

Filed:

May 6, 1986

Appl. No.:

3/260096

Inventors:

Jack I. Raffel - Lexington MA
John A. Yasaitis - Lexington MA
Glenn H. Chapman - Bedford MA
Mark L. Naiman - Lincoln MA
James A. Burns - Harvard MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 21265

US Classification:

437 19

Abstract:

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer and a second metal layer. Diffusion barrier may be employed between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

US Patent:

45854904, Apr 29, 1986

Filed:

Oct 3, 1984

Appl. No.:

6/657128

Inventors:

Jack I. Raffel - Lexington MA
John A. Yasaitis - Lexington MA
Glenn H. Chapman - Bedford MA
Mark L. Naiman - Lincoln MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 21265
B23K 2700

US Classification:

148 15

Abstract:

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

US Patent:

46364048, Jan 13, 1987

Filed:

Sep 17, 1984

Appl. No.:

6/651230

Inventors:

Jack I. Raffel - Lexington MA
John A. Yasaitis - Lexington MA
Glenn H. Chapman - Bedford MA

Assignee:

Mass. Institute of Technology - Cambridge MA

International Classification:

B05D 306
B05D 512
B23K 900

US Classification:

427 531

Abstract:

A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

US Patent:

50875892, Feb 11, 1992

Filed:

Jun 26, 1989

Appl. No.:

7/371587

Inventors:

Glenn H. Chapman - Bedford MA
Terry O. Herndon - Carlisle MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 2144

US Classification:

437195

Abstract:

A method of fabricating programmable interlayer conductive links in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more link regions of the insulative layer, forming at least one upper conductor over the implanted regions and selectively applying sufficient energy to at least one of the implanted regions of the integrated circuit structure to render the selected link region conductive. The invention also embraces customized integrated circuit structures with interlayer conductive paths made in accordance with this method.

US Patent:

48430340, Jun 27, 1989

Filed:

May 23, 1988

Appl. No.:

7/194720

Inventors:

Terry O. Herndon - Carlisle MA
Glenn H. Chapman - Bedford MA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

H01L 2144
H01L 2188

US Classification:

437189

Abstract:

A method of producing interlayer conductive paths having substantially planar top surfaces in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more selected regions of the insulative layer, forming at least one upper conductor over the selected regions and sintering the integrated circuit structure sufficient to render the selected regions conductive. The invention also embraces an integrated circuit structures with interlayer conductive paths made in accordance with this method.