Amd
Senior Member of Technical Staff
Intel Corporation Jan 2005 - Feb 2008
Not An Intel Employee
Hewlett-Packard Jan 1994 - Feb 2008
Engineer
Evans & Sutherland Aug 1983 - Dec 1993
Design Engineer
Education:
Rensselaer Polytechnic Institute 1979 - 1983
Bachelors, Bachelor of Science, Electrical Engineering
Glenn W. Strunk - Fort Collins CO Edmundo Rojas - Westminster CO Theodore G. Rossin - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06T 1530
US Classification:
345434
Abstract:
A system and method for performing view clipping and model clipping of graphics primitives in a geometry accelerator of a computer graphics system. The method includes performing view clipping and model clipping of the graphics primitives in homogeneous window coordinates. The geometry accelerator includes a transform machine, a light machine, a clipping machine, and a plane equation machine. The transform machine receives vertex data defining a graphics primitive, in object coordinates, and transforms the vertex data into homogeneous window coordinates. The light machine receives the transformed vertex data from the transform machine and enhances the transformed vertex data by simulating lighting conditions of the graphics primitive. The light machine provides light enhanced transformed vertex data to the clipping machine. The clipping machine receives the light enhanced vertex data from the light machine and determines intersections of edges of the graphics primitive with view clipping planes and with any user specified model clipping planes.
Rom-Based Control Unit In A Geometry Accelerator For A Computer Graphics System
Alan S. Krech - Fort Collins CO Theodore G. Rossin - Fort Collins CO Edmundo Rojas - Fort Collins CO Michael S McGrath - Fort Collins CO Ted Rakel - Fort Collins CO Glenn W Strunk - Fort Collins CO Jon L Ashburn - Fort Collins CO S Paul Tucker - Ft Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.
Theodore G. Rossin - Fort Collins CO Edmundo Rojas - Fort Collins CO Glenn W. Strunk - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1500
US Classification:
345434
Abstract:
A system and method for reducing an amount of memory that is needed to perform view clipping and model clipping of an input primitive in a geometry accelerator of a computer graphics system. The method includes view clipping the input graphics primitive with each view clipping boundary to determine a view-clipped geometry, storing view-clipped vertex data defining the view clipped geometry in memory, model clipping a view-clipped triangle forming the view-clipped geometry with each user defined model clipping plane to determine a model-clipped geometry, and storing model-clipped vertex data defining the model-clipped geometry in the memory in the memory locations previously occupied by said view-clipped vertex data. The method is repeated until each view-clipped triangle forming the view-clipped geometry has been model-clipped.
Centralized Branch Intelligence System And Method For A Geometry Accelerator
Alan S. Krech - Fort Collins CO Theodore G. Rossin - Fort Collins CO Glenn W Strunk - Fort Collins CO Michael S McGrath - Fort Collins CO Edmundo Rojas - Fort Collins CO S Paul Tucker - Fort Collins CO Jon L Ashburn - Fort Collins CO Ted Rakel - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.
Assembler System And Method For A Geometry Accelerator
An assembler system enables efficient usage of space in a read only memory (ROM) that permits multiway instruction branching. Source code is analyzed and assembled by the assembler system and the assembler system then efficiently places the instructions in the ROM. The source code includes at least the following elements or an equivalent counterpart thereof: next state statements, nonaligned instructions, align statements, and aligned instructions. Next state statements serve as a flag to separate the various instructions. Nonaligned instructions are defined as those instructions that are nonaddressable by other instructions, i. e. , those instructions that are not branched to. Align statements serve as a flag to the assembler system that a plurality k (where k is equal to 2. sup. n and where n is a positive integer) of aligned instructions directly follow in succession. Furthermore, aligned instructions are defined as those that are addressable by a plurality of other instructions, i. e.
Rom-Based Control Units In A Geometry Accelerator For A Computer Graphics System
Alan S. Krech - Fort Collins CO Theodore G. Rossin - Fort Collins CO Edmundo Rojas - Fort Collins CO Michael S McGrath - Fort Collins CO Ted Rakel - Fort Collins CO Glenn W Strunk - Fort Collins CO Jon L Ashburn - Fort Collins CO S Paul Tucker - Fort Collins CO
Assignee:
Hewlett-Packard Co. - Palo Alto CA
International Classification:
G06F 1516
US Classification:
345503
Abstract:
The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e. g. , an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc. ) and a plurality of control units (e. g. , a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc. ) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.
System And Method For Speculative Execution In A Geometry Accelerator
Alan S. Krech - Fort Collins CO Glenn W Strunk - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1580
US Classification:
345505
Abstract:
A system and method for performing speculative execution of state machine operation in a graphics accelerator. In accordance with one aspect of the invention, the method includes the step of executing steps in a first state machine that is operating on a graphic primitive. As is known, a graphic primitive is defined by a plurality of vertices. In accordance with the invention, the preferred embodiment receives the coordinate parameters for the second to last primitive vertex. Then it evaluates one or more conditions that indicate whether steps in a second state machine need to be executed, based upon parameters of primitive vertices already received. It then branches to and begins executing steps in another state machine, based upon the tentative conditions, and continuing execution of the steps in the transformation state machine in parallel with the continued execution of the steps in the another state machine. After a predetermined number of states, the method reevaluates the one or more conditions, at which time the value of the one or more conditions is no longer tentative, but determinative of the next state information. Then, the method invokes a reset condition, aborts execution of the steps in the another state machine, and returns execution to a predetermined step in the first state machine, if the one or more conditions of the evaluating and reevaluating steps are inconsistent.