Gong M Chen

US Patent:

6509247, Jan 21, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/769710

Inventors:

Gong Chen - Gilbert AZ
Robert D. Colclasure - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2176

US Classification:

438401, 438462, 438946, 438975

Abstract:

A semiconductor wafer ( ) includes a first semiconductor die ( ) having a first alignment mark ( ) disposed in an alignment region ( ) to align the first semiconductor die on the wafer. A second semiconductor die ( ) has a second alignment mark ( ) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.

US Patent:

62287435, May 8, 2001

Filed:

May 4, 1998

Appl. No.:

9/072052

Inventors:

Gong Chen - Gilbert AZ
Robert D. Colclasure - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2176

US Classification:

438401

Abstract:

A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.

US Patent:

62182005, Apr 17, 2001

Filed:

Jul 14, 2000

Appl. No.:

9/616152

Inventors:

Gong Chen - Gilbert AZ
Robert D. Colclasure - Apache Junction AZ
Wayne M. Paulson - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2166
G01R 3126

US Classification:

438 14

Abstract:

A multi-level registration control system for a photolithography process includes a photolithography device that prints first, second and third layers on a wafer. A first overlay mark defines overlay errors in a first direction between the first and third layer. The first overlay mark also defines overlay errors between the second and third layers. An overlay measurement device measures the overlay errors and generates an overlay signal. A feedback controller is connected to the overlay measurement device and the photolithography device. The feedback controller receives the overlay error signal and generates and transmits an alignment correction signal to the photolithography device. The first overlay mark is a box-in-box overlay mark or a frame-in-frame overlay mark. By providing a single overlay mark to align three layers, the multi-layer overlay control system reduces scribe grid area and saves useful silicone surface area.