Gong C Ouyang from Redmond, WA, age 49

view source

Location:

Redmond, WA

Work:

Microsoft
Hardware Engineer

Fine Feature Formation Techniques For Printed Circuit Boards
view source
US Patent:

20190098764, Mar 28, 2019
Filed:

Apr 2, 2016
Appl. No.:

16/081487
Inventors:

- Santa Clara CA, US
Kemal Aygun - Tempe AZ, US
Kai Xiao - Portland OR, US
Gong Ouyang - Olympia WA, US
Zhichao Zhang - Chandler AZ, US
Assignee:

INTEL CORPORATION - Santa Clara CA
International Classification:

H05K 3/00
H05K 1/02
H05K 3/02
Abstract:

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region within the conductive structure. Other embodiments are described and claimed.

Fine-Featured Traces For Integrated Circuit Package Support Structures
view source
US Patent:

20180174940, Jun 21, 2018
Filed:

Dec 19, 2016
Appl. No.:

15/383858
Inventors:

- Santa Clara CA, US
Gong Ouyang - Olympia WA, US
Russell S. Aoki - Tacoma WA, US
Zhichao Zhang - Chandler AZ, US
Kai Xiao - University Place WA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 23/34
H01L 23/373
H01L 23/498
Abstract:

Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.

Helically Insulated Twinax Cable Systems And Methods
view source
US Patent:

20170287591, Oct 5, 2017
Filed:

Apr 1, 2016
Appl. No.:

15/088924
Inventors:

Zhichao Zhang - Chandler AZ, US
Gong Ouyang - Olympia WA, US
Kai Xiao - University Place WA, US
Eric J. Li - Chandler AZ, US
Kemal Aygun - Chandler AZ, US
International Classification:

H01B 7/02
H01B 13/08
H01B 13/22
H05K 9/00
Abstract:

A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.

Compact Via Structures And Method Of Making Same
view source
US Patent:

20160378215, Dec 29, 2016
Filed:

Jun 26, 2015
Appl. No.:

14/752642
Inventors:

- Santa Clara CA, US
Raul Enriquez Shibayama - Zapopan, MX
Gong Ouyang - Olympia WA, US
Jose Diego Guillen Gonzalez - Guadalajara, MX
International Classification:

G06F 3/041
H01P 3/08
Abstract:

Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.

Inductors For Circuit Board Through Hole Structures
view source
US Patent:

20160276091, Sep 22, 2016
Filed:

Mar 21, 2015
Appl. No.:

14/664827
Inventors:

- Santa Clara CA, US
Gong Ouyang - Olympia WA, US
Kai Xiao - University Place WA, US
Kemal Aygun - Chandler AZ, US
Assignee:

INTEL CORPORATION - Santa Clara CA
International Classification:

H01F 27/28
H05K 3/30
H05K 1/11
H01F 41/04
H05K 1/18
Abstract:

Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

Inductors For Circuit Board Through Hole Structures
view source
US Patent:

20160276092, Sep 22, 2016
Filed:

Apr 3, 2015
Appl. No.:

14/678714
Inventors:

- Santa Clara CA, US
Gong Ouyang - Olympia WA, US
Kai Xiao - University Place WA, US
Kemal Aygun - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01F 27/28
H05K 1/18
H05K 1/02
H05K 1/11
Abstract:

Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

Shielding A Connector To Reduce Interference
view source
US Patent:

20150340817, Nov 26, 2015
Filed:

May 23, 2014
Appl. No.:

14/286494
Inventors:

Xiang Li - Portland OR, US
Hao-Han Hsu - Portland OR, US
Yun Ling - Portland OR, US
Gong Ouyang - Olympia WA, US
Kai Xiao - University Place WA, US
Jiangqi He - Mesa AZ, US
Wei Xu - Chandler AZ, US
International Classification:

H01R 13/6598
H01R 43/18
H05K 3/36
H01R 12/72
H05K 3/28
Abstract:

In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

Broadside Coupled Differential Design
view source
US Patent:

20150333387, Nov 19, 2015
Filed:

May 15, 2014
Appl. No.:

14/278330
Inventors:

KAI XIAO - University Place WA, US
RAUL ENRIQUEZ SHIBAYAMA - Zapopan, MX
GONG OUYANG - Olympia WA, US
International Classification:

H01P 3/08
H01P 11/00
Abstract:

A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.